公开(公告)号：US6141324A

公开(公告)日：2000-10-31

申请号：US145194

申请日：1998-09-01

申请人： Ben Abbott ,  Rajesh Chhabria ,  Abhijit Dey

发明人： Ben Abbott ,  Rajesh Chhabria ,  Abhijit Dey

IPC分类号： H04L29/08 ,  H04J20060101 ,  H04J3/14 ,  H04M3/00 ,  H04Q7/38

CPC分类号： H04L47/2416 ,  H04L47/263 ,  H04L47/283 ,  H04M7/006

摘要： A low latency, high throughput communication system applicable to real-time communications, such as real-time audio and video, controls the total in-transit data between a transmitting application and a receiving application to a target amount using feedback. As a result, the system operates at about the same throughput as it does when modem and other buffers associated with the system are always full, but at a substantially lower latency and with the modem and other buffers less than full. The system is applicable to both modem-to-modem telephone communications and internet communications in accordance with the TCP and UDP protocols. The system includes a forward error correction and retransmission scheme for use with the UDP protocol, and also includes a scheduling protocol for use in association with virtual channels.

摘要翻译： 适用于实时通信（例如实时音频和视频）的低延迟，高吞吐量通信系统使用反馈将发送应用和接收应用之间的总转接数据控制到目标量。 因此，系统以与系统相关的调制解调器和其他缓冲区始终为空，但处于实质上较低的延迟并且调制解调器和其他缓冲器小于满的操作以大致相同的吞吐量运行。 该系统适用于调制解调器到调制解调器的电话通信和根据TCP和UDP协议的互联网通信。 该系统包括与UDP协议一起使用的前向纠错和重传方案，并且还包括与虚拟信道相关联使用的调度协议。

公开(公告)号：US20100180100A1

公开(公告)日：2010-07-15

申请号：US12319934

申请日：2009-01-13

申请人： Tsung-Hsin Lu ,  Carl Alberola ,  Rajesh Chhabria ,  Zhenyu Zhou

发明人： Tsung-Hsin Lu ,  Carl Alberola ,  Rajesh Chhabria ,  Zhenyu Zhou

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30141 ,  G06F9/3824 ,  G06F9/3828 ,  G06F12/0862 ,  G06F13/28

摘要： A microprocessor includes a direct access memory (DMA) engine which is responsive to pairs of block indices associated with one or more blocks in a first logical plane and transfers the one or more blocks between the first logical plane, a second logical plane, and a physical memory space according to the pairs of block indices. The logical planes represent two dimensional fields of data such as those found in images and videos. The microprocessor further comprises cache memory which updates its content with one or more cache-blocks which are in the neighborhood of the one or more blocks improving the operation of the cache memory by increasing cache hits. The DMA engine may further operate on n-dimensional blocks in a n-dimensional logical space. The microprocessor further includes special-purpose instructions, operative on a single-instruction-multiple-data (SIMD) computation unit, especially tailored to perform matrix operations. The SIMD may share scalar operands with an onboard single-instruction-single-data (SISD) computation unit.

摘要翻译： 微处理器包括直接访问存储器（DMA）引擎，其响应于与第一逻辑平面中的一个或多个块相关联的块索引对，并且在第一逻辑平面，第二逻辑平面和第二逻辑平面之间传送一个或多个块 物理内存空间根据块索引对。 逻辑平面表示数据的二维字段，例如在图像和视频中找到的数据。 微处理器还包括高速缓存存储器，其通过一个或多个块附近的一个或多个高速缓存块更新其内容，通过增加高速缓存命中来改善高速缓冲存储器的操作。 DMA引擎还可以在n维逻辑空间中对n维块进行操作。 微处理器还包括在单指令多数据（SIMD）计算单元上操作的特殊用途指令，特别适于执行矩阵操作。 SIMD可以与板载单指令单数据（SISD）计算单元共享标量操作数。