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公开(公告)号：US09222973B2
公开(公告)日：2015-12-29
申请号：US13355265
申请日：2012-01-20
申请人： Benedikt Geukes , Bodo Hoppe , Matteo Michel , Juergen Wakunda
发明人： Benedikt Geukes , Bodo Hoppe , Matteo Michel , Juergen Wakunda
IPC分类号： G06F21/00 , G01R31/317 , G01R31/3185
CPC分类号： G06F21/72 , G01R31/31719 , G01R31/3177 , G01R31/318588 , G06F21/76
摘要： Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.
摘要翻译： 一些实施例包括用于处理集成电路中的扫描链的方法。 该方法可以包括：在集成电路中接收扫描链，其中扫描链包括秘密密钥图案; 将秘密密钥图案与扫描链分离; 将秘密密钥模式与参考密钥模式进行比较; 基于将所述秘密密钥图案与所述参考密钥图案进行比较来确定所述秘密密钥图案与所述参考密钥图案不匹配; 以及产生指示所述秘密密钥图案与所述参考键图案不匹配的信号。
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公开(公告)号：US20120191403A1
公开(公告)日：2012-07-26
申请号：US13355265
申请日：2012-01-20
申请人： Benedikt Geukes , Bodo Hoppe , Matteo Michel , Juergen Wakunda
发明人： Benedikt Geukes , Bodo Hoppe , Matteo Michel , Juergen Wakunda
IPC分类号： G06F19/00
CPC分类号： G06F21/72 , G01R31/31719 , G01R31/3177 , G01R31/318588 , G06F21/76
摘要： Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.
摘要翻译： 一些实施例包括用于处理集成电路中的扫描链的方法。 该方法可以包括：在集成电路中接收扫描链，其中扫描链包括秘密密钥图案; 将秘密密钥图案与扫描链分离; 将秘密密钥模式与参考密钥模式进行比较; 基于将所述秘密密钥图案与所述参考密钥图案进行比较来确定所述秘密密钥图案与所述参考密钥图案不匹配; 以及产生指示所述秘密密钥图案与所述参考键图案不匹配的信号。
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公开(公告)号：US20080216030A1
公开(公告)日：2008-09-04
申请号：US12060953
申请日：2008-04-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefor. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of:a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.
摘要翻译： 本发明涉及一种用于验证数字逻辑电路及其程序产品的正确操作的系统。 为了在功能，详尽的仿真和符号仿真领域添加有用的替代方案，提出了执行以下步骤：a）用除位值之外的附加属性标记网，其中所述位值和 所述额外财产在特定时间在所述净值有效; b）根据一组预定的语义规则传播网络的标记，其中根据预定的模拟定义所述一组预定语义规则; 以及c）在所述数字逻辑电路的预定下游位置处产生输出，所述输出提供信息，如果或者不是所述属性已经通过所述电路传播到所述预定下游位置。
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公开(公告)号：US20130110490A1
公开(公告)日：2013-05-02
申请号：US13285460
申请日：2011-10-31
申请人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
发明人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F11/202 , G06F11/2242 , G06F17/5022 , G06F2217/68
摘要： A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.
摘要翻译： 模拟环境验证模拟处理器内核中的处理器维护功能。 仿真环境为模拟处理器核心执行第一次仿真。 在仿真期间，仿真环境创建一个模拟转储文件。 在稍后的时间点，仿真环境为模拟处理器核心执行第二次仿真。 模拟环境节省了模拟处理器内核的状态。 然后，仿真环境通过加载先前创建的仿真模型转储文件来替代模拟处理器内核的状态。 然后，仿真环境将模拟处理器核心的状态设置为执行处理器备用代码，并恢复第二次仿真。
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公开(公告)号：US07213220B2
公开(公告)日：2007-05-01
申请号：US11009350
申请日：2004-12-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to the field of computer hardware locic circuits, and in particular to a method for verifying the proper operation of a digital logic circuit, and in particular to symbolic simulation of a gate-level netlist corresponding to said hardware logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) analyzing symbolic expressions visible at predetermined locations within said logic; b) determining, which nets in the netlist carry complex symbolic expressions, which comprise more than one symbol; c) replacing said complex expressions with a “crunshed color”, for cutting off said complex symbolic expression from further propagation through the netlist; d) continuing said symbolic simulation including said crunched color information on predetermined nets.
摘要翻译： 本发明涉及计算机硬件定位电路领域，特别涉及用于验证数字逻辑电路的正确操作的方法，特别涉及对应于所述硬件逻辑电路的门级网表的符号仿真。 为了在功能，详尽的仿真和符号仿真领域增加一个有用的替代方案，提出了执行以下步骤：a）分析在所述逻辑内的预定位置可见的符号表达式; b）确定网表中的网络携带多于一个符号的复杂符号表达式; c）用“重要颜色”代替所述复合表达式，以便将所述复杂符号表达式从进一步传播通过网表切断; d）继续所述符号模拟，其包括在预定网上的所述嘎吱嘎吱的颜色信息。
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公开(公告)号：US09015025B2
公开(公告)日：2015-04-21
申请号：US13285460
申请日：2011-10-31
申请人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
发明人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
CPC分类号： G06F17/5009 , G06F11/202 , G06F11/2242 , G06F17/5022 , G06F2217/68
摘要： A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.
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公开(公告)号：US07565636B2
公开(公告)日：2009-07-21
申请号：US12060953
申请日：2008-04-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefore. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.
摘要翻译： 本发明涉及一种用于验证数字逻辑电路和程序产品的正确操作的系统。 为了在功能，详尽的仿真和符号仿真领域添加有用的替代方案，提出了执行以下步骤：a）用除位值之外的附加属性标记网，其中所述位值和 所述额外财产在特定时间在所述净值有效; b）根据一组预定的语义规则传播网络的标记，其中根据预定的模拟定义所述一组预定语义规则; 以及c）在所述数字逻辑电路的预定下游位置处产生输出，所述输出提供信息，如果或者不是所述属性已经通过所述电路传播到所述预定下游位置。
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公开(公告)号：US07398494B2
公开(公告)日：2008-07-08
申请号：US11461469
申请日：2006-08-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation aim; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.
摘要翻译： 本发明涉及一种用于验证数字逻辑电路的正确操作的方法。 为了在功能，详尽的仿真和符号仿真领域添加有用的替代方案，提出了执行以下步骤：a）用除位值之外的附加属性标记网，其中所述位值和 所述额外财产在特定时间在所述净值有效; b）根据一组预定语义规则传播网络的标记，其中根据预定的模拟目标定义所述一组预定语义规则; 以及c）在所述数字逻辑电路的预定下游位置处产生输出，所述输出提供信息，如果或者不是所述属性已经通过所述电路传播到所述预定下游位置。
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公开(公告)号：US20070050739A1
公开(公告)日：2007-03-01
申请号：US11461469
申请日：2006-08-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than the bit value, both, bit value and additional property being valid at said net at a given time, b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the rules are defined according to a predetermined simulation aim, c) generating an output at a predetermined downstream location of the circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined circuit location.
摘要翻译： 本发明涉及一种用于验证数字逻辑电路的正确操作的方法。 为了在功能，详尽的仿真和符号仿真领域添加一个有用的替代方案，建议执行以下步骤：a）用除位值之外的附加属性标记网络，位值和附加值 属性在给定时间在所述网络处有效，b）根据一组预定语义规则传播网络的标记，其中根据预定的模拟目标定义规则，c）在预定的下游位置生成输出 所述输出提供信息，如果或者不是所述属性已经通过所述电路传播到所述预定电路位置。
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公开(公告)号：US20050138586A1
公开(公告)日：2005-06-23
申请号：US11009350
申请日：2004-12-10
CPC分类号： G06F17/5022
摘要： The present invention relates to the field of computer hardware locic circuits, and in particular to a method for verifying the proper operation of a digital logic circuit, and in particular to symbolic simulation of a gate-level netlist corresponding to said hardware logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) analyzing symbolic expressions visible at predetermined locations within said logic, b) determining, which nets in the netlist carry complex symbolic expressions, which comprise more than one symbol, c) replacing said complex expressions with a “crunshed color”, for cutting off said complex symbolic expression from further propagation through the netlist, d) continuing said symbolic simulation including said crunched color information on predetermined nets.
摘要翻译： 本发明涉及计算机硬件定位电路领域，特别涉及用于验证数字逻辑电路的正确操作的方法，特别涉及对应于所述硬件逻辑电路的门级网表的符号仿真。 为了在功能，详尽的仿真和符号仿真的领域中增加一个有用的替代方案，提出了执行以下步骤：a）分析在所述逻辑内的预定位置可见的符号表达式，b）确定在 网表携带复杂的符号表达式，其包含多于一个符号，c）用“重要颜色”替换所述复合表达式，用于切断所述复杂符号表达式以进一步传播通过网表，d）继续所述符号模拟，包括所述交替颜色 关于预定网络的信息。
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