公开(公告)号：US20130139014A1

公开(公告)日：2013-05-30

申请号：US13305498

申请日：2011-11-28

申请人： Benedikt Geukes ,  Matteo Michel ,  Carsten Schmitt ,  Manfred H. Walz

发明人： Benedikt Geukes ,  Matteo Michel ,  Carsten Schmitt ,  Manfred H. Walz

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318572 ,  G01R31/318561

摘要： In some embodiments, a computer-implemented method includes receiving, in a processor, a device description code identifying components of a device and connections between the components, wherein some of the components and connections form boundary cells used for testing the device. The method can include processing, in the processor, the device description code to determine that the components and the connections meet a standard governing components and connections necessary for the boundary cells. The method can also include traversing the connections between the components to determine that the connections meet the standard, and reporting, via one or more output devices, that the device complies with the standard.

摘要翻译： 在一些实施例中，计算机实现的方法包括在处理器中接收识别设备的组件和组件之间的连接的设备描述代码，其中组件和连接中的一些形成用于测试设备的边界单元。 该方法可以包括在处理器中处理设备描述码以确定组件和连接满足边界单元所必需的标准控制组件和连接。 该方法还可以包括遍历组件之间的连接以确定连接符合标准，并且经由一个或多个输出设备报告设备符合标准。

公开(公告)号：US08914693B2

公开(公告)日：2014-12-16

申请号：US13397544

申请日：2012-02-15

申请人： Martin Doerr ,  Benedikt Geukes ,  Holger Horbach ,  Matteo Michel ,  Manfred Walz

发明人： Martin Doerr ,  Benedikt Geukes ,  Holger Horbach ,  Matteo Michel ,  Manfred Walz

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/3185

CPC分类号： G01R31/3177 ,  G01R31/318552 ,  G01R31/318572 ,  G06F11/267

摘要： A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.

摘要翻译： 用于微处理器的扫描电路（JTAG 1149扩展）利用以比外部JTAG时钟更快的时钟速度工作的传输逻辑和扫描链。 传输逻辑将输入串行数据流（TDI）转换成输入数据包，将其发送到扫描链，并将输出数据包转换为输出数据流（TDO）。 传输逻辑包括具有分片输入缓冲器的解串器和具有分片输出缓冲器的串行器。 扫描电路可用于边界扫描锁存器的测试，或用于控制微处理器的内部功能。 本地时钟缓冲器可用于分配时钟信号，由外部时钟过采样产生的信号控制。 结果是JTAG扫描系统不受外部JTAG时钟速度的限制，允许多个内部扫描操作在单个外部JTAG周期内完成。

公开(公告)号：US08656235B2

公开(公告)日：2014-02-18

申请号：US13305498

申请日：2011-11-28

申请人： Benedikt Geukes ,  Matteo Michel ,  Carsten Schmitt ,  Manfred H. Walz

发明人： Benedikt Geukes ,  Matteo Michel ,  Carsten Schmitt ,  Manfred H. Walz

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318561

摘要： In some embodiments, a computer-implemented method includes receiving, in a processor, a device description code identifying components of a device and connections between the components, wherein some of the components and connections form boundary cells used for testing the device. The method can include processing, in the processor, the device description code to determine that the components and the connections meet a standard governing components and connections necessary for the boundary cells. The method can also include traversing the connections between the components to determine that the connections meet the standard, and reporting, via one or more output devices, that the device complies with the standard.

摘要翻译： 在一些实施例中，计算机实现的方法包括在处理器中接收识别设备的组件和组件之间的连接的设备描述代码，其中组件和连接中的一些形成用于测试设备的边界单元。 该方法可以包括在处理器中处理设备描述码以确定组件和连接满足边界单元所必需的标准控制组件和连接。 该方法还可以包括遍历组件之间的连接以确定连接符合标准，并且经由一个或多个输出设备报告设备符合标准。

公开(公告)号：US20130212445A1

公开(公告)日：2013-08-15

申请号：US13397544

申请日：2012-02-15

申请人： Martin Doerr ,  Benedikt Geukes ,  Holger Horbach ,  Matteo Michel ,  Manfred Walz

发明人： Martin Doerr ,  Benedikt Geukes ,  Holger Horbach ,  Matteo Michel ,  Manfred Walz

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/318552 ,  G01R31/318572 ,  G06F11/267

摘要： A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.

摘要翻译： 用于微处理器的扫描电路（JTAG 1149扩展）利用以比外部JTAG时钟更快的时钟速度工作的传输逻辑和扫描链。 传输逻辑将输入串行数据流（TDI）转换成输入数据包，将其发送到扫描链，并将输出数据包转换为输出数据流（TDO）。 传输逻辑包括具有分片输入缓冲器的解串器和具有分片输出缓冲器的串行器。 扫描电路可用于边界扫描锁存器的测试，或用于控制微处理器的内部功能。 本地时钟缓冲器可用于分配时钟信号，由外部时钟过采样产生的信号控制。 结果是JTAG扫描系统不受外部JTAG时钟速度的限制，允许多个内部扫描操作在单个外部JTAG周期内完成。

公开(公告)号：US20120191403A1

公开(公告)日：2012-07-26

申请号：US13355265

申请日：2012-01-20

申请人： Benedikt Geukes ,  Bodo Hoppe ,  Matteo Michel ,  Juergen Wakunda

发明人： Benedikt Geukes ,  Bodo Hoppe ,  Matteo Michel ,  Juergen Wakunda

IPC分类号： G06F19/00

CPC分类号： G06F21/72 ,  G01R31/31719 ,  G01R31/3177 ,  G01R31/318588 ,  G06F21/76

摘要： Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

摘要翻译： 一些实施例包括用于处理集成电路中的扫描链的方法。 该方法可以包括：在集成电路中接收扫描链，其中扫描链包括秘密密钥图案; 将秘密密钥图案与扫描链分离; 将秘密密钥模式与参考密钥模式进行比较; 基于将所述秘密密钥图案与所述参考密钥图案进行比较来确定所述秘密密钥图案与所述参考密钥图案不匹配; 以及产生指示所述秘密密钥图案与所述参考键图案不匹配的信号。

公开(公告)号：US09222973B2

公开(公告)日：2015-12-29

申请号：US13355265

申请日：2012-01-20

申请人： Benedikt Geukes ,  Bodo Hoppe ,  Matteo Michel ,  Juergen Wakunda

发明人： Benedikt Geukes ,  Bodo Hoppe ,  Matteo Michel ,  Juergen Wakunda

IPC分类号： G06F21/00 ,  G01R31/317 ,  G01R31/3185

CPC分类号： G06F21/72 ,  G01R31/31719 ,  G01R31/3177 ,  G01R31/318588 ,  G06F21/76

摘要： Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

摘要翻译： 一些实施例包括用于处理集成电路中的扫描链的方法。 该方法可以包括：在集成电路中接收扫描链，其中扫描链包括秘密密钥图案; 将秘密密钥图案与扫描链分离; 将秘密密钥模式与参考密钥模式进行比较; 基于将所述秘密密钥图案与所述参考密钥图案进行比较来确定所述秘密密钥图案与所述参考密钥图案不匹配; 以及产生指示所述秘密密钥图案与所述参考键图案不匹配的信号。