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公开(公告)号：US20060248377A1
公开(公告)日：2006-11-02
申请号：US11395575
申请日：2006-03-31
申请人： Bertan Tezcan , William Beane , Scott Darnell
发明人： Bertan Tezcan , William Beane , Scott Darnell
IPC分类号： G06F11/00
CPC分类号： H04L49/30 , H04L45/52 , H04L47/70 , H04L49/10 , H04L49/109 , H04L49/1546 , H04L49/251 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3063 , H04L49/35
摘要： A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.
摘要翻译： 分组交换集成电路芯片被配置为从多个外部源接收诸如与RapidIO TM兼容的分组的分组，并且将所接收的分组中的数据选择性地传递到多个外部接收者。 芯片被配置为不修改地传递第一接收到的分组，并且终止第二接收分组并且预处理其有效载荷以产生新的分组。 芯片可以被配置为对第二接收分组执行信号采样处理操作，例如比特扩展，比特截断，比特重排序和/或比特算术运算。 芯片还可以被配置为基于接收到的分组中的目的地地址管理第一和第二接收分组。
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公开(公告)号：US20060248376A1
公开(公告)日：2006-11-02
申请号：US11395570
申请日：2006-03-31
申请人： Bertan Tezcan , William Beane , Scott Darnell
发明人： Bertan Tezcan , William Beane , Scott Darnell
IPC分类号： G06F11/00
CPC分类号： H04L49/30 , H04L45/52 , H04L47/70 , H04L49/10 , H04L49/109 , H04L49/1546 , H04L49/251 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3063 , H04L49/35
摘要： A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.
摘要翻译： 分组处理集成电路芯片包括被配置为从相应的外部源接收分组的多个输入端口和被配置为向相应的外部接收者发送分组的多个输出端口。 芯片还包括可配置为从接收到的分组的有效载荷中提取数据的分组处理器，以处理所提取的数据以产生具有与外部接收者的数据结构兼容的格式的有效载荷的新分组，并将新分组传送到输出端口 。 芯片还可以包括分组交换结构，其被配置为将选择的分组从输入端口路由到选择的输出端口，而无需净荷修改。
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公开(公告)号：US20060248375A1
公开(公告)日：2006-11-02
申请号：US11394886
申请日：2006-03-31
申请人： Bertan Tezcan , William Beane , Scott Darnell , A. David MacAdam
发明人： Bertan Tezcan , William Beane , Scott Darnell , A. David MacAdam
IPC分类号： G06F11/00
CPC分类号： H04L49/30 , H04L45/52 , H04L47/70 , H04L49/10 , H04L49/109 , H04L49/1546 , H04L49/251 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3063 , H04L49/35
摘要： A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configured to process the received packets to generate new packets with new payloads according to selected ones of a plurality of packet processing scenarios based on destination addresses in the received packets. The plurality of packet processing scenarios may include individual packet processing scenarios and group packet processing scenarios that invoke parallel processing of a packet by selected ones of the individual packet processing scenarios. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.
摘要翻译： 分组处理集成电路芯片包括被配置为从相应的外部源接收分组的多个输入端口和被配置为向相应的外部接收者发送分组的多个输出端口。 该芯片还包括分组处理器，其被配置为根据接收到的分组中的目的地地址，根据多个分组处理场景中的选定的分组处理方案来处理接收到的分组以产生具有新有效载荷的新分组。 多个分组处理场景可以包括单独的分组处理场景和组分组处理场景，其通过所选择的各个分组处理场景调用分组的并行处理。 芯片还可以包括分组交换结构，其被配置为将选择的分组从输入端口路由到选择的输出端口，而无需净荷修改。
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公开(公告)号：US07882280B2
公开(公告)日：2011-02-01
申请号：US11395575
申请日：2006-03-31
CPC分类号： H04L49/30 , H04L45/52 , H04L47/70 , H04L49/10 , H04L49/109 , H04L49/1546 , H04L49/251 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3063 , H04L49/35
摘要： A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.
摘要翻译： 分组交换集成电路芯片被配置为从多个外部源接收诸如RapidIO TM兼容分组的分组，并且将所接收的分组中的数据选择性地传递到多个外部接收者。 芯片被配置为不修改地传递第一接收到的分组，并且终止第二接收分组并且预处理其有效载荷以产生新的分组。 芯片可以被配置为对第二接收分组执行信号采样处理操作，例如比特扩展，比特截断，比特重排序和/或比特算术运算。 芯片还可以被配置为基于接收到的分组中的目的地地址管理第一和第二接收分组。
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公开(公告)号：US07739424B2
公开(公告)日：2010-06-15
申请号：US11395570
申请日：2006-03-31
CPC分类号： H04L49/30 , H04L45/52 , H04L47/70 , H04L49/10 , H04L49/109 , H04L49/1546 , H04L49/251 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3063 , H04L49/35
摘要： A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.
摘要翻译： 分组处理集成电路芯片包括被配置为从相应的外部源接收分组的多个输入端口和被配置为向相应的外部接收者发送分组的多个输出端口。 芯片还包括可配置为从接收到的分组的有效载荷中提取数据的分组处理器，以处理所提取的数据以产生具有与外部接收者的数据结构兼容的格式的有效载荷的新分组，并将新分组传送到输出端口 。 芯片还可以包括分组交换结构，其被配置为将选择的分组从输入端口路由到选择的输出端口，而无需净荷修改。
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6.发明授权公开(公告)号：US07676675B2
公开(公告)日：2010-03-09
申请号：US10456235
申请日：2003-06-06
IPC分类号： H04L9/32
CPC分类号： H04L63/0272 , H04L63/083 , H04L63/104 , H04L63/166
摘要： Architecture for generating and maintaining a terminal services connection from an external client to an internal intranet client behind a firewall and/or router. The external user is first authenticated after which the external client is passed to a remote user portal. A listing of available internal computers is presented to the external client user, the selection of one that initiates an intranet server to create a listening socket thereon, and a socket on the selected internal client. The server creates a thread that manages the terminal services connection between the external client and the internal client by listening for traffic and forwarding the traffic between the ports.
摘要翻译： 用于生成和维护从外部客户端到防火墙和/或路由器后面的内部Intranet客户端的终端服务连接的架构。 首先对外部用户进行身份验证，之后将外部客户端传递到远程用户门户。 向外部客户端用户提供可用内部计算机的列表，选择启动Intranet服务器以在其上创建侦听套接字的内容，以及所选内部客户端上的套接字。 服务器创建一个线程，通过监听流量并在端口之间转发流量来管理外部客户端和内部客户端之间的终端服务连接。
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公开(公告)号：US20080056872A1
公开(公告)日：2008-03-06
申请号：US11849283
申请日：2007-09-01
申请人： Scott Darnell , David Gotter
发明人： Scott Darnell , David Gotter
IPC分类号： B66F11/00
CPC分类号： A61G3/06 , A61G3/062 , A61G7/1017
摘要： Disclosed is a system for lifting a wheelchair into and out of a vehicle. A bearing mount is fixed to the vehicle rotationally captures a pivot rod to which a rear mounting plate is fixed. Two pairs of parallel arms are pivotally fixed between the rear mounting plate and a front mounting plate, such that the arms and mounting plates form a parallelogram therebetween. A pair of forks are horizontally mounted to the forward mounting plate and are adapted to engage a pair of horizontal fork receivers that are fixed to the wheelchair. At least one vertical linear actuator is fixed between the mounting plates and is adapted to selectively raise and lower the forward mounting plate and forks with respect to the vehicle. At least one horizontal linear actuator is fixed between the vehicle and the rear mounting plate. The horizontal linear actuator is adapted to selectively rotate the forward mounting plate, arms, and the pair of forks between the inside and outside positions.
摘要翻译： 公开了一种用于将轮椅提升出车辆的系统。 轴承座固定在车辆上，旋转地捕获固定有后安装板的枢轴。 两对平行臂可枢转地固定在后安装板和前安装板之间，使得臂和安装板在它们之间形成平行四边形。 一对叉子水平地安装到前安装板上，并且适于接合一对固定在轮椅上的水平叉接收器。 至少一个垂直线性致动器固定在安装板之间，并且适于选择性地升高和降低前安装板和相对于车辆的叉。 至少一个水平线性致动器固定在车辆和后安装板之间。 水平线性致动器适于在内部和外部位置之间选择性地旋转前部安装板，臂和一对叉。
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