公开(公告)号：US08516163B2

公开(公告)日：2013-08-20

申请号：US11679820

申请日：2007-02-27

申请人： Chi-Lie Wang ,  Bertan Tezcan

发明人： Chi-Lie Wang ,  Bertan Tezcan

IPC分类号： G06F13/28 ,  G06F9/26

CPC分类号： G06F13/28

摘要： A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.

摘要翻译： 串行缓冲器包括配置为存储从主机接收的数据包的队列。 直接存储器访问（DMA）引擎从具有达到相应水印的水位的最高优先级队列接收数据分组。 DMA引擎被配置为响应于从多个DMA寄存器组中选择的DMA寄存器集合。 用于配置DMA引擎的DMA寄存器组可以响应于读取的数据分组的头部中的信息，或响应于读取数据分组的队列而被选择。 每个DMA寄存器集定义系统存储器中相应的缓冲区，数据包被传输到该缓冲区。 每个DMA寄存器集还定义相应的缓冲器是否以卷绕模式或停止模式被访问，以及是否响应于传送到相应缓冲器中的最后地址而生成门铃信号。

公开(公告)号：US07818470B2

公开(公告)日：2010-10-19

申请号：US11863192

申请日：2007-09-27

申请人： Chi-Lie Wang ,  Jason Z. Mo ,  Bertan Tezcan

发明人： Chi-Lie Wang ,  Jason Z. Mo ,  Bertan Tezcan

IPC分类号： G06F3/00

CPC分类号： H04L47/28 ,  H04L47/30 ,  H04L47/33 ,  H04L49/90

摘要： A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path.

摘要翻译： 串行缓冲器被配置为通过数据分组传送路径将多个接收到的数据分组发送到主机处理器。 串行缓冲器的门铃控制器通过数据包传送路径监视发送到主机处理器的数据包的数量，并估计主机处理器实际接收到的数据包的数量。 门铃控制器每当估计的数据分组数与帧中的固定数量的数据分组对应时，就产生门铃命令。 门铃命令在门铃命令路径上传送到主机处理器，该命令路径比数据包传送路径快。 门铃控制器可以响应于第一延迟值来估计主机处理器实际接收的数据分组的数量，其表示门铃命令路径比数据分组传送路径多得多的速度。

公开(公告)号：US07693040B1

公开(公告)日：2010-04-06

申请号：US11743080

申请日：2007-05-01

申请人： Harmeet Bhugra ,  Bertan Tezcan

发明人： Harmeet Bhugra ,  Bertan Tezcan

IPC分类号： H04J11/00

CPC分类号： H04L5/0007 ,  H04L27/2647

摘要： A baseband processor includes a processing switch for performing orthogonal frequency division multiplexing operations on data packets and routing the data packets in the baseband processor. Additionally, the baseband processor includes digital signal processors for performing symbol processing operations on the data packets. The baseband processor is scalable such that digital signal processors may be added to, or removed from, the baseband processor. Further, the baseband processor is programmable such that the symbol processing operations may be distributed among the digital signal processors.

摘要翻译： 基带处理器包括用于对数据分组执行正交频分复用操作并在基带处理器中路由数据分组的处理开关。 此外，基带处理器包括用于对数据分组执行符号处理操作的数字信号处理器。 基带处理器是可扩展的，使得数字信号处理器可以被添加到基带处理器或从基​​带处理器移除。 此外，基带处理器是可编程的，使得符号处理操作可以在数字信号处理器之间分配。

公开(公告)号：US20060248377A1

公开(公告)日：2006-11-02

申请号：US11395575

申请日：2006-03-31

申请人： Bertan Tezcan ,  William Beane ,  Scott Darnell

发明人： Bertan Tezcan ,  William Beane ,  Scott Darnell

IPC分类号： G06F11/00

CPC分类号： H04L49/30 ,  H04L45/52 ,  H04L47/70 ,  H04L49/10 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/3063 ,  H04L49/35

摘要： A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.

摘要翻译： 分组交换集成电路芯片被配置为从多个外部源接收诸如与RapidIO TM兼容的分组的分组，并且将所接收的分组中的数据选择性地传递到多个外部接收者。 芯片被配置为不修改地传递第一接收到的分组，并且终止第二接收分组并且预处理其有效载荷以产生新的分组。 芯片可以被配置为对第二接收分组执行信号采样处理操作，例如比特扩展，比特截断，比特重排序和/或比特算术运算。 芯片还可以被配置为基于接收到的分组中的目的地地址管理第一和第二接收分组。

公开(公告)号：US08213448B2

公开(公告)日：2012-07-03

申请号：US12043944

申请日：2008-03-06

申请人： Chi-Lie Wang ,  Jason Z. Mo ,  Calvin Nguyen ,  Bertan Tezcan

发明人： Chi-Lie Wang ,  Jason Z. Mo ,  Calvin Nguyen ,  Bertan Tezcan

IPC分类号： H04L12/54

CPC分类号： H04L1/0082 ,  H04L47/22 ,  H04L49/90

摘要： A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.

摘要翻译： 串行缓冲器监视传入的数据包流，以识别单个丢失的数据包和多个连续的丢失数据包。 在检测到多个连续丢失数据包时，产生中断，从而停止数据传输。 在检测到单个丢失的分组时，将单个丢失的分组标识符插入到分组的分组报头中，导致单个丢失分组的标识。 传入的数据包，包括任何插入的单个丢失的数据包标识符，被写入队列。 当水位达到队列的水位时，读取存储的数据包以创建输出数据包流。 当从队列读取的分组包括插入的单个丢失的分组标识符时，将虚拟分组（例如，具有全零的数据有效载荷的分组）插入到输出分组流中。 因此，实时应用能够以恒定的方式处理输出分组流。

公开(公告)号：US07739424B2

公开(公告)日：2010-06-15

申请号：US11395570

申请日：2006-03-31

申请人： Bertan Tezcan ,  William Terry Beane ,  Scott Darnell

发明人： Bertan Tezcan ,  William Terry Beane ,  Scott Darnell

IPC分类号： G06F3/00 ,  G06F11/00

CPC分类号： H04L49/30 ,  H04L45/52 ,  H04L47/70 ,  H04L49/10 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/3063 ,  H04L49/35

摘要： A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

摘要翻译： 分组处理集成电路芯片包括被配置为从相应的外部源接收分组的多个输入端口和被配置为向相应的外部接收者发送分组的多个输出端口。 芯片还包括可配置为从接收到的分组的有效载荷中提取数据的分组处理器，以处理所提取的数据以产生具有与外部接收者的数据结构兼容的格式的有效载荷的新分组，并将新分组传送到输出端口 。 芯片还可以包括分组交换结构，其被配置为将选择的分组从输入端口路由到选择的输出端口，而无需净荷修改。

公开(公告)号：US20060248375A1

公开(公告)日：2006-11-02

申请号：US11394886

申请日：2006-03-31

申请人： Bertan Tezcan ,  William Beane ,  Scott Darnell ,  A. David MacAdam

发明人： Bertan Tezcan ,  William Beane ,  Scott Darnell ,  A. David MacAdam

IPC分类号： G06F11/00

CPC分类号： H04L49/30 ,  H04L45/52 ,  H04L47/70 ,  H04L49/10 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/3063 ,  H04L49/35

摘要： A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configured to process the received packets to generate new packets with new payloads according to selected ones of a plurality of packet processing scenarios based on destination addresses in the received packets. The plurality of packet processing scenarios may include individual packet processing scenarios and group packet processing scenarios that invoke parallel processing of a packet by selected ones of the individual packet processing scenarios. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

摘要翻译： 分组处理集成电路芯片包括被配置为从相应的外部源接收分组的多个输入端口和被配置为向相应的外部接收者发送分组的多个输出端口。 该芯片还包括分组处理器，其被配置为根据接收到的分组中的目的地地址，根据多个分组处理场景中的选定的分组处理方案来处理接收到的分组以产生具有新有效载荷的新分组。 多个分组处理场景可以包括单独的分组处理场景和组分组处理场景，其通过所选择的各个分组处理场景调用分组的并行处理。 芯片还可以包括分组交换结构，其被配置为将选择的分组从输入端口路由到选择的输出端口，而无需净荷修改。

公开(公告)号：US06867991B1

公开(公告)日：2005-03-15

申请号：US10613245

申请日：2003-07-03

申请人： Bertan Tezcan ,  Michael Miller

发明人： Bertan Tezcan ,  Michael Miller

IPC分类号： G11C8/06 ,  G11C15/00

CPC分类号： G11C8/06 ,  G11C15/00

摘要： CAM devices and methods of operating CAM devices include mapping search word portions to partitions and virtual subpartitions in a CAM core. Some embodiments of the invention can provide, for example, a hybrid CAM device that includes a mapping circuit for implementing such partitioning and virtual subpartitioning that is implemented in memory, such as a random access memory (RAM) or a combination of CAM and RAM, that is integrated with the CAM core. In some embodiments, a CAM device includes a search word input, a CAM core comprising a plurality of CAM cells, and a virtual partitioning circuit that selectively enables a partition in the CAM core for search of a portion of a search word at the search word input responsive to the search word, and that provides a mapping of the search word to a comparand input to the CAM core. The mapping defines a virtual subpartition in the CAM core. The invention may be embodied as apparatus and methods.

摘要翻译： CAM设备和操作CAM设备的方法包括将搜索词部分映射到CAM内核中的分区和虚拟子分区。 本发明的一些实施例可以提供例如混合CAM设备，其包括用于实现在诸如随机存取存储器（RAM）或CAM和RAM的组合的存储器中实现的这种分区和虚拟子分区的映射电路， 它与CAM内核集成。 在一些实施例中，CAM设备包括搜索词输入，包括多个CAM单元的CAM核心以及虚拟分区电路，所述虚拟分区电路选择性地启用CAM核心中的分区，以搜索搜索词的搜索词的一部分 输入，其响应于搜索词，并且提供搜索词到与CAM核心的比较输入的映射。 映射定义了CAM核心中的虚拟子分区。 本发明可以体现为装置和方法。

公开(公告)号：US07882280B2

公开(公告)日：2011-02-01

申请号：US11395575

申请日：2006-03-31

申请人： Bertan Tezcan ,  William Terry Beane ,  Scott Darnell

发明人： Bertan Tezcan ,  William Terry Beane ,  Scott Darnell

IPC分类号： G06F3/00 ,  G06F11/00

CPC分类号： H04L49/30 ,  H04L45/52 ,  H04L47/70 ,  H04L49/10 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/3063 ,  H04L49/35

摘要： A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.

摘要翻译： 分组交换集成电路芯片被配置为从多个外部源接收诸如RapidIO TM兼容分组的分组，并且将所接收的分组中的数据选择性地传递到多个外部接收者。 芯片被配置为不修改地传递第一接收到的分组，并且终止第二接收分组并且预处理其有效载荷以产生新的分组。 芯片可以被配置为对第二接收分组执行信号采样处理操作，例如比特扩展，比特截断，比特重排序和/或比特算术运算。 芯片还可以被配置为基于接收到的分组中的目的地地址管理第一和第二接收分组。

公开(公告)号：US20090225770A1

公开(公告)日：2009-09-10

申请号：US12043944

申请日：2008-03-06

申请人： Chi-Lie Wang ,  Jason Z. Mo ,  Calvin Nguyen ,  Bertan Tezcan

发明人： Chi-Lie Wang ,  Jason Z. Mo ,  Calvin Nguyen ,  Bertan Tezcan

IPC分类号： H04L12/56

CPC分类号： H04L1/0082 ,  H04L47/22 ,  H04L49/90

摘要： A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.

摘要翻译： 串行缓冲器监视传入的数据包流，以识别单个丢失的数据包和多个连续的丢失数据包。 在检测到多个连续丢失数据包时，产生中断，从而停止数据传输。 在检测到单个丢失的分组时，将单个丢失的分组标识符插入到分组的分组报头中，导致单个丢失分组的识别。 传入的数据包，包括任何插入的单个丢失的数据包标识符，被写入队列。 当水位达到队列的水位时，读取存储的数据包以创建输出数据包流。 当从队列读取的分组包括插入的单个丢失的分组标识符时，将虚拟分组（例如，具有全零的数据有效载荷的分组）插入到输出分组流中。 因此，实时应用能够以恒定的方式处理输出分组流。