Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation

    公开(公告)号:US09952991B1

    公开(公告)日:2018-04-24

    申请号:US14690339

    申请日:2015-04-17

    CPC classification number: G06F13/28 G06F5/12 G06F5/14 G06F13/4068 H04L47/10

    Abstract: In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors. In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer; a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation; and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

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