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公开(公告)号：US10013373B1
公开(公告)日：2018-07-03
申请号：US15344537
申请日：2016-11-06
Applicant: BiTMICRO Networks, Inc.
CPC classification number: G06F13/28 , G06F13/1673 , G06F2213/2802
Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.
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公开(公告)号：US09916213B1
公开(公告)日：2018-03-13
申请号：US14688209
申请日：2015-04-16
Applicant: BiTMICRO Networks, Inc.
CPC classification number: G06F11/2007 , G06F11/2002 , G06F11/2005 , G06F11/2017 , G06F11/202 , G06F11/2023 , G06F11/2041 , G06F13/1605 , G06F13/366 , G06F13/4031
Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
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公开(公告)号：US09501436B1
公开(公告)日：2016-11-22
申请号：US14217041
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
IPC: G06F13/28
CPC classification number: G06F13/28 , G06F13/1673 , G06F2213/2802
Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.
Abstract translation: 在本发明的实施例中，提出了一种使用二级链表描述符机制来在闪存，存储器和IO控制器模块之间传递信息的方法。 该方法包括为一个或多个第一级描述符创建第一级数据结构; 为一个或多个第二级描述符创建第二级数据结构，每个第二级描述符具有指向跟踪信息的指针，所述跟踪信息包括数据DMA的开始信息，运行信息和倒带信息; 使用一个或多个第二级描述符，一个或多个第一级描述符和数据DMA的跟踪信息; 在数据DMA期间更新跟踪信息; 并在数据DMA结束时更新跟踪信息。
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公开(公告)号：US20140289441A1
公开(公告)日：2014-09-25
申请号：US14297628
申请日：2014-06-06
Applicant: BiTMICRO Networks, Inc.
IPC: G06F13/16
CPC classification number: G06F13/1657 , G06F12/00 , G06F12/0246 , G06F13/1673 , G06F13/1684 , G06F13/36
Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
Abstract translation: 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。
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公开(公告)号：US10423554B1
公开(公告)日：2019-09-24
申请号：US15790299
申请日：2017-10-23
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Cyrill Coronel Ponce , Jarmie Dela Cruz Espuerta
IPC: G06F13/20 , G06F13/366 , G06F13/00
Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.
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Patent Agency Ranking
公开(公告)号：US09798688B1
公开(公告)日：2017-10-24
申请号：US14216627
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Cyrill Coronel Ponce , Jarmie Dela Cruz Espuerta
IPC: G06F13/20 , G06F13/366 , G06F13/00
CPC classification number: G06F13/366
Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.
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公开(公告)号：US10459842B1
公开(公告)日：2019-10-29
申请号：US15904322
申请日：2018-02-24
Applicant: BiTMICRO Networks, Inc.
Inventor： Rey H. Bruce , Ricardo H. Bruce , Marlon B. Verdan , Elsbeth Lauren Tagayo-Villapaña
IPC: G06F12/0862 , G06F9/38 , G06F13/16 , G06F3/06 , G06F13/28
Abstract: In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.
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公开(公告)号：US10430303B1
公开(公告)日：2019-10-01
申请号：US15891147
申请日：2018-02-07
Applicant: BITMICRO Networks, Inc.
Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
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9.发明授权公开(公告)号：US09952991B1
公开(公告)日：2018-04-24
申请号：US14690339
申请日：2015-04-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Marlon B. Verdan , Rowenah Michelle Jago-on
IPC: G06F5/12 , G06F13/28 , G06F13/40 , H04L12/801 , G06F5/14
CPC classification number: G06F13/28 , G06F5/12 , G06F5/14 , G06F13/4068 , H04L47/10
Abstract: In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors. In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer; a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation; and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.
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公开(公告)号：US09875205B1
公开(公告)日：2018-01-23
申请号：US14217161
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Jarmie De La Cruz Espuerta , Marlon Basa Verdan
CPC classification number: G06F13/4031 , G06F13/385 , G06F13/4027
Abstract: A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.
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