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    Bus arbitration with routing and failover mechanism
    1.
    发明授权
    Bus arbitration with routing and failover mechanism 有权

    公开(公告)号：US10423554B1

    公开(公告)日：2019-09-24

    申请号：US15790299

    申请日：2017-10-23

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Ricardo H. Bruce ,  Cyrill Coronel Ponce ,  Jarmie Dela Cruz Espuerta

    IPC: G06F13/20 ,  G06F13/366 ,  G06F13/00

    Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

    Bus arbitration with routing and failover mechanism
    3.
    发明授权
    Bus arbitration with routing and failover mechanism 有权

    公开(公告)号：US09798688B1

    公开(公告)日：2017-10-24

    申请号：US14216627

    申请日：2014-03-17

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Ricardo H. Bruce ,  Cyrill Coronel Ponce ,  Jarmie Dela Cruz Espuerta

    IPC: G06F13/20 ,  G06F13/366 ,  G06F13/00

    CPC classification number: G06F13/366

    Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

    Write buffering
    4.
    发明授权
    Write buffering 有权

    公开(公告)号：US09734067B1

    公开(公告)日：2017-08-15

    申请号：US14689045

    申请日：2015-04-16

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Rolando H. Bruce ,  Elmer Paule Dela Cruz ,  Mark Ian Alcid Arcedera

    IPC: G06F12/0831 ,  G06F12/0875

    CPC classification number: G06F12/0833 ,  G06F11/1076 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0844 ,  G06F12/0868 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/217 ,  G06F2212/225 ,  G06F2212/313 ,  G06F2212/452 ,  G06F2212/62

    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.

    Valid Data Compression On SSD
    5.
    发明申请
    Valid Data Compression On SSD 审中-公开
    SSD上的有效数据压缩

    公开(公告)号：US20160224464A1

    公开(公告)日：2016-08-04

    申请号：US15002329

    申请日：2016-01-20

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Marvin Dela Cruz Fenol ,  Jik-Jik Oyong Abed ,  Precious Nezaiah Umali Pestano ,  Benedict Centeno Bantigue ,  Joevannl Baliton Parairo

    IPC: G06F12/02 ,  G06F12/06 ,  G06F3/06

    CPC classification number: G06F12/0246 ,  G06F12/0646 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/7202 ,  G06F2212/7205 ,  G06F2212/7206

    Abstract: In an embodiment of the invention, a method comprises: obtaining a first data block with a lowest number of valid data from a block record; moving a first valid data in a first memory data area of the first data block to a first pre-erased memory data area in a second data block; and moving a second valid data in a second memory data area in the first data block to a second pre-erased memory data area in the second data block. In another embodiment of the invention, an article of manufacture comprises: a non-transient computer-readable medium having stored thereon instructions that are configured to: obtain a first data block with a lowest number of valid data from a block record; move a first valid data in a first memory data area of the first data block to a first pre-erased memory data area in a second data block; and move a second valid data in a second memory data area in the first data block to a second pre-erased memory data area in the second data block. In yet another embodiment of the invention, an apparatus comprises: a data storage system configured to: obtain a first data block with a lowest number of valid data from a block record; move a first valid data in a first memory data area of the first data block to a first pre-erased memory data area in a second data block; and move a second valid data in a second memory data area in the first data block to a second pre-erased memory data area in the second data block.

    Abstract translation: 在本发明的实施例中，一种方法包括：从块记录获得具有最低数量的有效数据的第一数据块; 将第一数据块的第一存储器数据区中的第一有效数据移动到第二数据块中的第一预擦除存储器数据区; 以及将所述第一数据块中的第二存储器数据区域中的第二有效数据移动到所述第二数据块中的第二预擦除存储器数据区域。 在本发明的另一个实施例中，制品包括：非瞬态计算机可读介质，其上存储有指令，其被配置为：从块记录获得具有最低数量的有效数据的第一数据块; 将第一数据块的第一存储器数据区域中的第一有效数据移动到第二数据块中的第一预擦除存储器数据区域; 并且将第一数据块中的第二存储器数据区域中的第二有效数据移动到第二数据块中的第二预擦除存储器数据区域。 在本发明的另一个实施例中，一种装置包括：数据存储系统，被配置为：从块记录获得具有最低数量的有效数据的第一数据块; 将第一数据块的第一存储器数据区域中的第一有效数据移动到第二数据块中的第一预擦除存储器数据区域; 并且将第一数据块中的第二存储器数据区域中的第二有效数据移动到第二数据块中的第二预擦除存储器数据区域。

    Write buffering
    6.
    发明授权
    Write buffering 有权

    公开(公告)号：US10445239B1

    公开(公告)日：2019-10-15

    申请号：US15665321

    申请日：2017-07-31

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Rolando H. Bruce ,  Elmer Paule Dela Cruz ,  Mark Ian Alcid Arcedera

    IPC: G06F12/0831 ,  G06F12/0875

    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.

    Multi-level message passing descriptor
    7.
    发明授权
    Multi-level message passing descriptor 有权

    公开(公告)号：US10013373B1

    公开(公告)日：2018-07-03

    申请号：US15344537

    申请日：2016-11-06

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Ricardo H. Bruce ,  Bernard Sherwin Leung Chiw ,  Margaret Anne Nadonga Somera

    IPC: G06F13/28 ,  G06F13/16

    CPC classification number: G06F13/28 ,  G06F13/1673 ,  G06F2213/2802

    Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.

    Multi-level message passing descriptor
    9.
    发明授权
    Multi-level message passing descriptor 有权
    多级消息传递描述符

    公开(公告)号：US09501436B1

    公开(公告)日：2016-11-22

    申请号：US14217041

    申请日：2014-03-17

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Ricardo H. Bruce ,  Bernard Sherwin Leung Chiw ,  Margaret Anne Nadonga Somera

    IPC: G06F13/28

    CPC classification number: G06F13/28 ,  G06F13/1673 ,  G06F2213/2802

    Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.

    Abstract translation: 在本发明的实施例中，提出了一种使用二级链表描述符机制来在闪存，存储器和IO控制器模块之间传递信息的方法。 该方法包括为一个或多个第一级描述符创建第一级数据结构; 为一个或多个第二级描述符创建第二级数据结构，每个第二级描述符具有指向跟踪信息的指针，所述跟踪信息包括数据DMA的开始信息，运行信息和倒带信息; 使用一个或多个第二级描述符，一个或多个第一级描述符和数据DMA的跟踪信息; 在数据DMA期间更新跟踪信息; 并在数据DMA结束时更新跟踪信息。

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