公开(公告)号：US20080195919A1

公开(公告)日：2008-08-14

申请号：US11865856

申请日：2007-10-02

申请人： Bok-gue Park ,  Uk-song Kang ,  Sang-jae Rhee

发明人： Bok-gue Park ,  Uk-song Kang ,  Sang-jae Rhee

IPC分类号： H03M13/03

CPC分类号： H03M13/19 ,  G06F11/1044 ,  H03M13/611

摘要： A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

摘要翻译： 半导体存储器件包括存储单元阵列和纠错码（ECC）引擎。 存储单元阵列在其中存储正常数据和奇偶校验数据的位。 ECC引擎在掩蔽模式中执行掩蔽操作，ECC引擎使用正常数据来计算奇偶校验数据。 正常数据包括要被更新的第一部分和将被掩蔽操作保存的第二部分。

公开(公告)号：US08132086B2

公开(公告)日：2012-03-06

申请号：US11865856

申请日：2007-10-02

申请人： Bok-gue Park ,  Uk-song Kang ,  Sang-jae Rhee

发明人： Bok-gue Park ,  Uk-song Kang ,  Sang-jae Rhee

IPC分类号： G06F11/00

CPC分类号： H03M13/19 ,  G06F11/1044 ,  H03M13/611

摘要： A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

摘要翻译： 半导体存储器件包括存储单元阵列和纠错码（ECC）引擎。 存储单元阵列在其中存储正常数据和奇偶校验数据的位。 ECC引擎在掩蔽模式中执行掩蔽操作，ECC引擎使用正常数据来计算奇偶校验数据。 正常数据包括要被更新的第一部分和将被掩蔽操作保存的第二部分。

公开(公告)号：US20080082870A1

公开(公告)日：2008-04-03

申请号：US11902261

申请日：2007-09-20

申请人： Bok-gue Park

发明人： Bok-gue Park

IPC分类号： G06F11/00

CPC分类号： G06F11/1008

摘要： Example embodiments are directed to a parallel bit test device and method using error correcting code. The parallel bit test device may include an error detecting and correcting unit configured to count the number of fail bits in an m-bit data signal, for example, by comparing bits of the m-bit data signal with corresponding bits of expected data, where m is a positive integer, and to output correction signals. The error detecting and correcting unit may be further configured to perform at least one logic operation on a correction control signal and comparison signals. The correction control signal may be generated in response to a test mode register set (TMRS) signal set and input by a user such that the logic level of the correction control signal may vary according to the counted number of fail bits. Each comparison signal may include information about a fail bit and the address of the fail bit.

摘要翻译： 示例性实施例涉及使用纠错码的并行位测试装置和方法。 并行比特测试装置可以包括错误检测和校正单元，其被配置为对m比特数据信号中的失败比特数进行计数，例如通过比较m比特数据信号的比特与预期数据的相应比特，其中 m是正整数，并输出校正信号。 误差检测和校正单元还可以被配置为对校正控制信号和比较信号执行至少一个逻辑运算。 校正控制信号可以响应于由用户设置并输入的测试模式寄存器组（TMRS）信号产生，使得校正控制信号的逻辑电平可以根据计数的失败位数而变化。 每个比较信号可以包括关于故障位和故障位的地址的信息。