公开(公告)号：US20060040481A1

公开(公告)日：2006-02-23

申请号：US10919571

申请日：2004-08-17

Applicant: Bor-Wen Chan ,  Yu-Shen Lai

Inventor： Bor-Wen Chan ,  Yu-Shen Lai

IPC: H01L21/3205

CPC classification number: H01L29/66545 ,  H01L29/66507 ,  H01L29/6656

Abstract: Methods and structures for preventing salicidation are disclosed. A substrate has an gate electrode on it. Spacers are on sidewalls of the gate electrode, exposing a top portion of the gate electrode. A dielectric layer is formed above the spacers, covering the exposed top portion of the gate electrode. Methods and structures for forming source and drain salicidation are disclosed. They further salicidize source and drain regions which are adjacent to the spacers without forming salicidation on the gate electrode while salicidizing the source and drain regions. Methods and structures for forming gate electrode salicidation are also disclosed. They further form another dielectric layer covering the salicidized source and drain regions. A portion of the dielectric layer is removed so as to expose a top surface of the gate electrode. The gate electrode is then salicidized.

Abstract translation: 公开了防止盐化的方法和结构。 衬底上具有栅电极。 隔板位于栅电极的侧壁上，露出栅电极的顶部。 在间隔物的上方形成介电层，覆盖露出的栅电极顶部。 公开了用于形成源极和漏极盐析的方法和结构。 它们进一步对与间隔物相邻的源极和漏极区域进行盐化，而不会在栅电极上形成水化，同时对源极和漏极区域进行盐化。 还公开了形成栅电极盐析的方法和结构。 它们进一步形成覆盖水化源极和漏极区域的另一个介电层。 去除电介质层的一部分以露出栅电极的顶表面。 然后将栅电极进行水杨酸化。

公开(公告)号：US07381619B2

公开(公告)日：2008-06-03

申请号：US10832679

申请日：2004-04-27

Applicant: Chih-Hao Wang ,  Yu-Shen Lai

Inventor： Chih-Hao Wang ,  Yu-Shen Lai

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A semiconductor device having dual work-function structures, such as dual work-function gate electrodes of transistors. In the preferred embodiment in which NMOS and PMOS transistors are formed on a semiconductor device, the transistors are initially formed with a dummy gate electrode and a dummy dielectric layer. The dummy gate electrode and dummy dielectric layers are removed. A gate dielectric layer and a first electrode layer are formed. A nitridation process is performed on the NMOS transistor to reduce the work function of the gate electrode. A second electrode layer is then formed on the first electrode layer.

Abstract translation: 具有双工作功能结构的半导体器件，例如晶体管的双工作功能栅电极。 在其中在半导体器件上形成NMOS和PMOS晶体管的优选实施例中，晶体管最初由伪栅极电极和虚设电介质层形成。 去除虚拟栅极电极和虚拟电介质层。 形成栅介电层和第一电极层。 在NMOS晶体管上进行氮化处理以降低栅电极的功函数。 然后在第一电极层上形成第二电极层。

公开(公告)号：US20050253173A1

公开(公告)日：2005-11-17

申请号：US10832679

申请日：2004-04-27

Applicant: Chih-Hao Wang ,  Yu-Shen Lai

Inventor： Chih-Hao Wang ,  Yu-Shen Lai

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A semiconductor device having dual work-function structures, such as dual work-function gate electrodes of transistors. In the preferred embodiment in which NMOS and PMOS transistors are formed on a semiconductor device, the transistors are initially formed with a dummy gate electrode and a dummy dielectric layer. The dummy gate electrode and dummy dielectric layers are removed. A gate dielectric layer and a first electrode layer are formed. A nitridation process is performed on the NMOS transistor to reduce the work function of the gate electrode. A second electrode layer is then formed on the first electrode layer.

Abstract translation: 具有双工作功能结构的半导体器件，例如晶体管的双工作功能栅电极。 在其中在半导体器件上形成NMOS和PMOS晶体管的优选实施例中，晶体管最初由伪栅极电极和虚设电介质层形成。 去除虚拟栅极电极和虚拟电介质层。 形成栅介电层和第一电极层。 在NMOS晶体管上进行氮化处理以降低栅电极的功函数。 然后在第一电极层上形成第二电极层。