公开(公告)号：US20100306634A1

公开(公告)日：2010-12-02

申请号：US12473885

申请日：2009-05-28

申请人： Bradford C. Lincoln

发明人： Bradford C. Lincoln

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： G11B20/1833 ,  G11B2020/1843 ,  G11B2220/2516 ,  G11B2220/415

摘要： An XOR unit is provided in a hard disk controller for calculating an XOR of two operands stored in a buffer memory. The XOR unit includes an XOR calculator for calculating the XOR of the operands and a CRC of the XOR resulting from the calculation. An XOR buffer is also included in the XOR unit for storing the XOR result and the CRC of the XOR result, and a CRC calculator for calculating a CRC of the XOR result stored in the XOR buffer. The CRC calculated by the CRC calculator is compared with the CRC of the XOR result stored in the CRC buffer to determine whether the XOR result has been corrupted in the XOR buffer. The XOR result stored in the XOR buffer is determined to be corrupted if the CRC calculated by the CRC calculator and the CRC stored in the XOR buffer do not match.

摘要翻译： 在硬盘控制器中提供XOR单元，用于计算存储在缓冲存储器中的两个操作数的异或。 XOR单元包括用于计算操作数的异或的XOR计算器和由计算产生的XOR的CRC。 异或缓冲器也包含在XOR单元中，用于存储XOR结果和XOR结果的CRC，以及用于计算存储在XOR缓冲器中的XOR结果的CRC的CRC计算器。 将由CRC计算器计算出的CRC与存储在CRC缓冲器中的XOR结果的CRC进行比较，以确定异或结果是否在XOR缓冲器中被破坏。 如果由CRC计算器计算的CRC和存储在XOR缓冲区中的CRC不匹配，则XOR缓冲区中存储的XOR结果被确定为已损坏。

公开(公告)号：US6075790A

公开(公告)日：2000-06-13

申请号：US764692

申请日：1996-12-11

申请人： Bradford C. Lincoln ,  David R. Meyer

发明人： Bradford C. Lincoln ,  David R. Meyer

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5681

摘要： A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the host periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.

摘要翻译： 主机中的状态队列和分段和重组（SAR）子系统中的控制队列位于控制平面中的主机总线的相对侧。 主机和SAR中的缓冲区描述符和主机中的缓冲区位于数据平面中。 为了将信元有效载荷传送到与SAR相连接的第一行，主机写入SAR具有这样的信元有效载荷。 主机将主机缓冲区描述符写入控制队列，以获得缓冲区有效载荷到第一行的传输。 传输完成后，SAR写状态队列。 为了将单元有效载荷传送到主机存储器，主机向控制队列写入从SAR接收有效负载的缓冲器的地址。 然后，SAR将缓冲区描述符写入状态队列，以获得单元有效负载到缓冲区的传输。 每个控制和状态队列可以分别被认为构成两（2）个控制队列和两个（2）状态队列。 SAR通过将由SAR写入的地址与这样的状态队列进行比较，由主机周期性地向主机处于状态队列的SAR写入地址，确定状态队列是否满。 主机通过将由主机写入这样的控制队列的地址与由SAR所写入的地址周期性地向SAR控制队列中的主机进行比较来确定是否任一个控制队列满。

公开(公告)号：US5991265A

公开(公告)日：1999-11-23

申请号：US756950

申请日：1996-12-02

申请人： Bradford C. Lincoln

发明人： Bradford C. Lincoln

IPC分类号： H04Q3/00 ,  H04L12/56 ,  H04Q11/04 ,  H04J3/02

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5635 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04L2012/5681 ,  Y10S370/905

摘要： An ATM system transmits different types of cells (data, forward resource management (RM) and backward RM) from station A through switch(es) to station B. Different fields in an Available Bit Rate (ABR) table provide controls over the rate of such cell transmissions. First particular field values in such table control the selection of successive ones of cell decision blocks which determine the type of cell to be transmitted. Second particular field values in such table control the selection of one of a plurality of entries in an exponent table which also provides other parameter values controlling the generation of an explicit rate. Third particular field values in the ABR table control the selection of an individual one of a plurality of rate decision blocks each indicating an individual rate of cell transmission from the station A to the station B. Each of the rate decision blocks includes a plurality of fields which control changes from the individual one of the rate decision blocks to a rate decision block generally providing a reduced rate of cell transmission. These changes are dependent in part upon the relative times for the reception and transmission by the station of the different types of cells. One step in controlling the cell transmission rate is to select the lower one of the explicit rate and the rate indicated in the individual one of the rate decision blocks.

摘要翻译： ATM系统通过交换机向站B发送从站A到站B的不同类型的小区（数据，前向资源管理（RM）和反向RM）。可用比特率（ABR）表中的不同字段提供对 这样的小区传输。 这种表格中的第一特定字段值控制确定要发送的单元的类型的连续的单元决策块的选择。 这种表格中的第二特定字段值控制指数表中多个条目之一的选择，该指数表还提供控制显式速率生成的其他参数值。 ABR表中的第三特定字段值控制多个速率判定块中的各个速率判定块的选择，每个速率判定块指示从站A到站B的单元传输的单独速率。每个速率判定块包括多个字段 其控制从速率判决块中的单个速率决定块到通常提供小区传输速率降低的速率判决块的变化。 这些变化部分地取决于台站对不同类型的小区的接收和传输的相对时间。 控制小区传输速率的一个步骤是选择速率决定块中个别速率中指示的较​​低的一个显式速率和速率。

公开(公告)号：US5949781A

公开(公告)日：1999-09-07

申请号：US467311

申请日：1995-06-06

申请人： Bradford C. Lincoln ,  Douglas M. Brady ,  David R. Meyer ,  Warner B. Andrews, Jr.

发明人： Bradford C. Lincoln ,  Douglas M. Brady ,  David R. Meyer ,  Warner B. Andrews, Jr.

IPC分类号： H04Q3/00 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L2012/561 ,  H04L2012/5616 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5679

摘要： A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions. When more than one (1) cell is scheduled at the same position, one (1) cell is transferred on a preset priority basis to the corresponding time slot. The other cells are delayed for transfer subsequently in idle time slots (i.e. no cell normally scheduled) in the same or other priorities. The cell delays for each source are accumulated to a maximum preset value. When the cell delays accumulated for a source exceed the normal time spacing between cells from that source, a cell the source transfers a cell in an idle time slot prior to the normally scheduled time slot to compensate for such delay.

摘要翻译： 单元格中的标题和有效负载被分离以在单元接口和主机存储器之间传送。 标题被传送到控制存储器。 为了传输到主机存储器，控制存储器最初提供主机 - 存储器区域地址和区域长度。 有效载荷记录在这样的区域。 当有效载荷长度超过第一地址区域中的有效载荷长度时，控制存储器还提供第二主机 - 存储器区域地址和长度。 为了从主机存储器传送到单元接口，控制存储器提供主机存储器区域地址，并且报头组合报头和有效载荷，并将组合传递到单元接口。 来自不同来源（即终端）的小区根据其个人传送速率被安排在表位置。 预定位置处的单元通常在对应于这些位置的时隙中传送。 当多于一个（1）小区被调度在相同位置时，一（1）个小区以预设的优先级被传送到相应的时隙。 在相同或其他优先级中，其他小区被延迟以在空闲时隙（即，没有小区正常安排）中传送。 每个源的单元延迟被累积到最大预设值。 当来自源的单元延迟超过来自该源的单元之间的正常时间间隔时，源单元在正常调度的时隙之前的空闲时隙中传送单元以补偿这种延迟。

公开(公告)号：US07009981B1

公开(公告)日：2006-03-07

申请号：US09433850

申请日：1999-11-04

申请人： Bradford C. Lincoln ,  David R. Meyer

发明人： Bradford C. Lincoln ,  David R. Meyer

IPC分类号： H04L12/28

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5681

摘要： A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the host periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.

公开(公告)号：US06301226B1

公开(公告)日：2001-10-09

申请号：US09416240

申请日：1999-10-12

申请人： Bradford C. Lincoln

发明人： Bradford C. Lincoln

IPC分类号： H04J302

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5635 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04L2012/5681 ,  Y10S370/905

摘要： An ATM system transmits different types of cells (data, forward resource management (RM) and backward RM) from station A through switch(es) to station B. Different fields in an Available Bit Rate (ABR) table provide controls over the rate of such cell transmissions. First particular field values in such table control the selection of successive ones of cell decision blocks which determine the type of cell to be transmitted. Second particular field values in such table control the selection of one of a plurality of entries in an exponent table which also provides other parameter values controlling the generation of an explicit rate. Third particular field values in the ABR table control the selection of an individual one of a plurality of rate decision blocks each indicating an individual rate of cell transmission from the station A to the station B. Each of the rate decision blocks includes a plurality of fields which control changes from the individual one of the rate decision blocks to a rate decision block generally providing a reduced rate of cell transmission. These changes are dependent in part upon the relative times for the reception and transmission by the station of the different types of cells. One step in controlling the cell transmission rate is to select the lower one of the explicit rate and the rate indicated in the individual one of the rate decision blocks. By providing these controls, an optimal, but not excessive, rate is selected to transmit the different cells.

摘要翻译： ATM系统通过交换机向站B发送从站A到站B的不同类型的小区（数据，前向资源管理（RM）和反向RM）。可用比特率（ABR）表中的不同字段提供对 这样的小区传输。 这种表格中的第一特定字段值控制确定要发送的单元的类型的连续的单元决策块的选择。 这种表格中的第二特定字段值控制指数表中多个条目之一的选择，该指数表还提供控制显式速率生成的其他参数值。 ABR表中的第三特定字段值控制多个速率判定块中的各个速率判定块的选择，每个速率判定块指示从站A到站B的单元传输的单独速率。每个速率判定块包括多个字段 其控制从速率判决块中的单个速率决定块到通常提供小区传输速率降低的速率判决块的变化。 这些变化部分地取决于台站对不同类型的小区的接收和传输的相对时间。 控制小区传输速率的一个步骤是选择速率决定块中个别速率中指示的较​​低的一个显式速率和速率。 通过提供这些控制，选择最佳但不是过多的速率来传送不同的单元。

公开(公告)号：US06223242B1

公开(公告)日：2001-04-24

申请号：US09161923

申请日：1998-09-28

申请人： Stephen J. Sheafor ,  Christopher Koerner ,  Bradford C. Lincoln ,  Robert Sugar ,  Jonathan L. Huie

发明人： Stephen J. Sheafor ,  Christopher Koerner ,  Bradford C. Lincoln ,  Robert Sugar ,  Jonathan L. Huie

IPC分类号： G06F1300

CPC分类号： H04L49/25 ,  H04L49/101 ,  H04L49/1538 ,  H04L49/45

摘要： A crossbar routing arrangement is disclosed for use in a digital system having three or more buses. An associated method is also disclosed. The routing arrangement is configured for transferring a set of data received from any particular one of the buses to any other selected one of the buses and includes a control arrangement associated with each bus for dividing the set of data into at least first and second subsets of data and for adding self-routing signals to each data subset which signals identify the selected bus. A switching arrangement is configured for directing the first and second data subsets in a predetermined way responsive to the self-routing signals. The control arrangement cooperates with the switching arrangement to transfer the data subsets over physically distinct data transfer paths defined between the switching arrangement and the control arrangements. In accordance with one feature, the configuration of the routing arrangement provides for linear expansion whereby to service buses having increased width and/or to service an increased number of buses in a cost effective manner while, in either instance, maintaining high data throughput.

摘要翻译： 公开了一种用于具有三个或更多个总线的数字系统中的横梁路由布置。 还公开了一种相关联的方法。 路由布置被配置为将从总线中的任何特定一个总线接收的一组数据传送到总线中的任何其他所选择的总线，并且包括与每个总线相关联的控制装置，用于将该组数据分成至少第一和第二子集 数据和用于将每个数据子集添加自路由信号，信号标识所选择的总线。 交换装置被配置为响应于自路由信号以预定方式引导第一和第二数据子集。 控制装置与切换装置配合以将数据子集传送到在切换装置和控制装置之间限定的物理不同的数据传输路径上。 根据一个特征，路由布置的配置提供线性扩展，从而以成本有效的方式服务具有增加的宽度和/或服务于增加数量的总线的总线，而在任一情况下维持高数据吞吐量。

公开(公告)号：US6005866A

公开(公告)日：1999-12-21

申请号：US109801

申请日：1998-07-02

申请人： Bradford C. Lincoln

发明人： Bradford C. Lincoln

IPC分类号： H04Q3/00 ,  H04L12/56 ,  H04Q11/04 ,  H04L12/28

CPC分类号： H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5636 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/5681

摘要： An asynchronous transfer mode scheduler schedules connection utilizing available bit rate (ABR) modes of traffic, unspecified bit rate (UBR) modes of traffic, variable bit rate (VBR) modes of traffic, and constant bit rate (CBR) modes of traffic. The scheduler communicates with a dynamic schedule table which includes a programmable number of slots. Each slot includes a CBR entry, a tunnel entry, and a number of VBR entries. The VBR entries store a slot tail pointer which indicates the end of a linked list. The scheduler utilizes the single bucket algorithm or dual bucket algorithm to dynamically schedule connections on future slots. The scheduler places connections using the VBR mode of traffic in a priority queue and takes the highest priority connection in the priority queue for transmission on the network.

公开(公告)号：US08266499B2

公开(公告)日：2012-09-11

申请号：US12473885

申请日：2009-05-28

申请人： Bradford C. Lincoln

发明人： Bradford C. Lincoln

IPC分类号： H03M13/00

CPC分类号： G11B20/1833 ,  G11B2020/1843 ,  G11B2220/2516 ,  G11B2220/415

摘要： An XOR unit is provided in a hard disk controller for calculating an XOR of two operands stored in a buffer memory. The XOR unit includes an XOR calculator for calculating the XOR of the operands and a CRC of the XOR resulting from the calculation. An XOR buffer is also included in the XOR unit for storing the XOR result and the CRC of the XOR result, and a CRC calculator for calculating a CRC of the XOR result stored in the XOR buffer. The CRC calculated by the CRC calculator is compared with the CRC of the XOR result stored in the CRC buffer to determine whether the XOR result has been corrupted in the XOR buffer. The XOR result stored in the XOR buffer is determined to be corrupted if the CRC calculated by the CRC calculator and the CRC stored in the XOR buffer do not match.

摘要翻译： 在硬盘控制器中提供XOR单元，用于计算存储在缓冲存储器中的两个操作数的异或。 XOR单元包括用于计算操作数的异或的XOR计算器和由计算产生的XOR的CRC。 异或缓冲器也包含在XOR单元中，用于存储XOR结果和XOR结果的CRC，以及用于计算存储在XOR缓冲器中的XOR结果的CRC的CRC计算器。 将由CRC计算器计算出的CRC与存储在CRC缓冲器中的XOR结果的CRC进行比较，以确定异或结果是否在XOR缓冲器中被破坏。 如果由CRC计算器计算的CRC和存储在XOR缓冲区中的CRC不匹配，则XOR缓冲区中存储的XOR结果被确定为已损坏。

公开(公告)号：US20080155296A1

公开(公告)日：2008-06-26

申请号：US11644052

申请日：2006-12-22

申请人： Michael James ,  Bradford C. Lincoln ,  Jason Molgaard

发明人： Michael James ,  Bradford C. Lincoln ,  Jason Molgaard

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

摘要： Apparatus for controlling input clock signals to a microprocessor includes a clock generator for generating the input clock signals to the microprocessor, and a clock controller for producing a control signal for disabling the clock generator from outputting the input clock signals to the microprocessor for a predetermined time. The clock generator resumes outputting the input clock signals to the microprocessor after the predetermined time.

摘要翻译： 用于将输入时钟信号控制到微处理器的装置包括用于产生到微处理器的输入时钟信号的时钟发生器和用于产生禁止时钟发生器的控制信号的时钟控制器，用于将输入时钟信号输出到微处理器预定的时间 。 时钟发生器在预定时间之后恢复输出到微处理器的输入时钟信号。