公开(公告)号：US6118378A

公开(公告)日：2000-09-12

申请号：US969928

申请日：1997-11-28

申请人： Brent F. Balch ,  Stephen W. Embling ,  Ming-Ren Lian

发明人： Brent F. Balch ,  Stephen W. Embling ,  Ming-Ren Lian

IPC分类号： G01V3/10 ,  G08B13/24 ,  H04Q1/00

CPC分类号： G01V3/105 ,  G08B13/2474

摘要： A single antenna transmits and receives signals. The single antenna has first and second antenna loops substantially lying in a common plane and partially overlapping. First and second transceiver circuits are coupled to the first and second antenna loops respectively, for respectively generating in a first mode of operation first and second pulsed magnetic fields together defining an interrogation zone for a marker generating a characteristic response to the magnetic fields in the interrogation zone, and for receiving signals from the interrogation zone in a second mode of operation. The first and second transceiver circuits alternately generate the first and second magnetic fields substantially in phase with one another and substantially out of phase with one another. The partially overlapping antenna loops prevent detuning of the transceivers otherwise resulting from the phase alternating. Each of the first and second transceiver circuits has a phase controllable transmitter section and a phase controllable receiver section. A controller independently phase controls the transmitter and receiver sections. Each receiver section is coupled across the tuned circuit of its respective transceiver circuit.

摘要翻译： 单个天线发射和接收信号。 单个天线具有基本上位于公共平面中并且部分重叠的第一和第二天线回路。 第一和第二收发器电路分别耦合到第一和第二天线回路，用于分别在第一和第二脉冲磁场中产生第一和第二脉冲磁场，这一定义了用于产生对询问中的磁场的特征响应的标记的询问区 并且用于在第二操作模式中从询问区接收信号。 第一和第二收发器电路交替地产生彼此基本上同相并且基本上彼此不同相的第一和第二磁场。 部分重叠的天线环路防止收发器失谐，否则由相位交替产生。 第一和第二收发器电路中的每一个具有相位可控发射器部分和相位可控的接收器部分。 控制器独立地控制发射器和接收器部分。 每个接收器部分耦合在其各自的收发器电路的调谐电路上。

公开(公告)号：US5969659A

公开(公告)日：1999-10-19

申请号：US980324

申请日：1997-11-28

申请人： Brent F. Balch ,  Stephen W. Embling ,  Fadi Ayoub ,  David Fallin

发明人： Brent F. Balch ,  Stephen W. Embling ,  Fadi Ayoub ,  David Fallin

IPC分类号： H03M1/18 ,  H03M1/12

CPC分类号： H03M1/186

摘要： An arrangement for improving the operation of an analog to digital converter (A/D), which can form part of an integrated circuit, the A/D converter being coupled to a reference voltage and having a plurality of input pins associated therewith comprises: a resistor divider having a plurality of resistors coupled in series, the resistor divider having an upper node coupled to a source of voltage to be converted, having a lower node coupled to a source of reference potential and having a plurality of intermediate nodes; and, each of the upper intermediate nodes being coupled to a respective one of the input pins of the A/D converter. The A/D converter can have enhanced resolution and/or an extended dynamic range when the voltage level being tested is divided arid the reference voltage is reduced. A corresponding method comprises the steps of: successively scaling down a voltage to be converted to a series of stepped down voltage levels; applying the successively stepped down voltage levels to respective ones of the input pins; and, sequentially scanning and acquiring a plurality of scaled A/D converter values from the input pins.

摘要翻译： 一种用于改进模拟数字转换器（A / D）的操作的装置，其可以形成集成电路的一部分，所述A / D转换器耦合到参考电压并且具有与其相关联的多个输入引脚的装置包括： 电阻器分压器具有串联耦合的多个电阻器，所述电阻器分压器具有耦合到要转换的电压源的上部节点，具有耦合到参考电位源并具有多个中间节点的下部节点; 并且每个上部中间节点耦合到A / D转换器的相应一个输入引脚。 当测试的电压电平被分配时，A / D转换器可以具有增强的分辨率和/或扩展的动态范围，并且减小参考电压。 相应的方法包括以下步骤：连续地缩小要转换成一系列降压电压的电压; 将相继降低的电压电平施加到相应的输入引脚; 并且从输入引脚顺序地扫描和获取多个缩放的A / D转换器值。