公开(公告)号：US20210240344A1

公开(公告)日：2021-08-05

申请号：US17162796

申请日：2021-01-29

申请人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

发明人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

IPC分类号： G06F3/06

摘要： Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).