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18 条记录 (耗时 0.019 秒)

    LDPC architecture
    1.
    发明授权
    LDPC architecture 有权
    LDPC架构

    公开(公告)号：US07353444B2

    公开(公告)日：2008-04-01

    申请号：US11123671

    申请日：2005-05-06

    申请人： Patrick A. Owsley ,  Brian A. Banister ,  Tom Hansen

    发明人： Patrick A. Owsley ,  Brian A. Banister ,  Tom Hansen

    IPC分类号： H03M13/45

    CPC分类号： H03M13/6561 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/45

    摘要： The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratios in a single operation, as opposed to the two pass traditionally associated with the Tanner Graphs. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISOs. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

    摘要翻译： 本发明涉及一种前向误差检测系统，特别适用于低密度奇偶校验码。 并行SISO结构允许解码器同时处理多个奇偶校验方程。 存在一种新的SISO解码器，其允许在单个操作中更新对数似然比，而不是传统上与Tanner图相关联的两遍。 在解码器中，存在一个映射结构，使得存储的估计，存储的差异和SISO正确对齐。 还可以处理同时处理的同一数据的多个实例。 这种结构以这样的方式管理更新和差异，即将并行处理的单个数据上的所有计算都并入正确的新更新估计中。

    SISO decoder
    2.
    发明授权
    SISO decoder 有权
    SISO解码器

    公开(公告)号：US07415659B2

    公开(公告)日：2008-08-19

    申请号：US11123672

    申请日：2005-05-06

    申请人： Brian A. Banister ,  Patrick A. Owsley ,  Tom Hansen

    发明人： Brian A. Banister ,  Patrick A. Owsley ,  Tom Hansen

    IPC分类号： H03M13/00

    CPC分类号： H03M13/6561 ,  H03M13/1105 ,  H03M13/1117 ,  H03M13/1122 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/45

    摘要： The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratio's in a single operation, as opposed to the two pass traditionally associated with the Tanner Graph's. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISO's. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

    摘要翻译： 本发明涉及一种前向误差检测系统，特别适用于低密度奇偶校验码。 并行SISO结构允许解码器同时处理多个奇偶校验方程。 有一个新的SISO解码器，允许在单个操作中更新对数似然比，而不是传统上与Tanner Graph相关联的两遍。 在解码器中，存在一个映射结构，可以正确对齐所存储的估计值，存储的差值和SISO。 还可以处理同时处理的同一数据的多个实例。 这种结构以这样的方式管理更新和差异，即将并行处理的单个数据上的所有计算都并入正确的新更新估计中。

    Generating dynamic huffman codes
    7.
    发明授权
    Generating dynamic huffman codes 有权
    生成动态huffman代码

    公开(公告)号：US07609182B2

    公开(公告)日：2009-10-27

    申请号：US12124945

    申请日：2008-05-21

    申请人： Patrick A. Owsley ,  Brian Banister ,  Jason Franklin

    发明人： Patrick A. Owsley ,  Brian Banister ,  Jason Franklin

    IPC分类号： H03M7/40

    CPC分类号： H03M7/40

    摘要： Huffman trees may be rapidly and effectively created by sorting a plurality of nodes by weight in an insertion sorter stack, popping the two lowest weighted nodes from the insertion sorter stack, forming a branch node from the popped entries, and placing the branch node into the insertion sorter.

    摘要翻译： 可以通过在插入分拣机堆栈中按重量排序多个节点来快速有效地创建霍夫曼树，从插入分拣机堆栈中弹出两个最低加权节点，从弹出的条目形成分支节点，并将分支节点放入 插入分拣机。

    Adaptive data compression system with systolic string matching logic
    8.
    发明授权
    Adaptive data compression system with systolic string matching logic 失效
    具有收缩字符串匹配逻辑的自适应数据压缩系统

    公开(公告)号：US5532693A

    公开(公告)日：1996-07-02

    申请号：US259760

    申请日：1994-06-13

    申请人： Kel D. Winters ,  Patrick A. Owsley ,  Catherine A. French ,  Robert M. Bode ,  Peter S. Feeley

    发明人： Kel D. Winters ,  Patrick A. Owsley ,  Catherine A. French ,  Robert M. Bode ,  Peter S. Feeley

    IPC分类号： G06F7/02 ,  G06T9/00 ,  H03K3/037 ,  H03K3/356 ,  H03M7/30

    CPC分类号： G06F7/02 ,  G06T9/005 ,  H03K3/037 ,  H03K3/356156 ,  H03M7/3086

    摘要： An adaptive lossless data compression system with systolic string matching logic performs compression and decompression at the maximum rate of one symbol per clock cycle. The adaptive data compression system uses an improvement of the LZ1 algorithm. A content addressable memory (CAM) is used to store the last n input symbols. The CAM is stationary, stored data is not shifted throughout the CAM, but rather the CAM is used as a circular queue controlled by a Write Address Pointer Counter (WREN). During a compression operation, a new input symbol may be written to the CAM on each clock cycle, while simultaneously the rest of the CAM is searched for the input symbol. Associated with each word of the CAM array is a String Match State Machine (SMSM) and, an address logic module (ALM). These modules detect the occurrence of strings stored in the CAM array that match the current input string and report the address of the longest matching string nearest to the Write Address Pointer. The SMSM modules constitute a systolic logic array, where state information is shifted synchronously in the direction of the Write Address Pointer. The strings are represented by a string code which includes a length value, representing the length of the string, and a position value, representing the position in the CAM of the beginning of the string. During a decompression operation, the single symbols and string codes are input to the system. The symbols are stored in the CAM and the control logic outputs the decompressed data symbols using the stored data and the string codes.

    摘要翻译： 具有收缩串匹配逻辑的自适应无损数据压缩系统以每个时钟周期的一个符号的最大速率执行压缩和解压缩。 自适应数据压缩系统使用LZ1算法的改进。 内容可寻址存储器（CAM）用于存储最后n个输入符号。 CAM是静止的，存储的数据不会在整个CAM中移动，而是CAM被用作由写地址指针计数器（WREN）控制的循环队列。 在压缩操作期间，可以在每个时钟周期将新的输入符号写入CAM，同时搜索CAM的其余部分来输入符号。 与CAM阵列的每个单词相关联的是字符串匹配状态机（SMSM）和地址逻辑模块（ALM）。 这些模块检测存储在CAM阵列中与当前输入字符串相匹配的字符串的出现，并报告最接近写入地址指针的最长匹配字符串的地址。 SMSM模块构成收缩逻辑阵列，其中状态信息在写地址指针的方向上同步移位。 字符串由字符串代码表示，字符串代码包括表示字符串长度的长度值和表示字符串开头的CAM中的位置的位置值。 在解压缩操作期间，单个符号和字符串代码被输入到系统。 符号存储在CAM中，控制逻辑使用存储的数据和字符串代码来输出解压缩的数据符号。