公开(公告)号：US5327571A

公开(公告)日：1994-07-05

申请号：US104398

申请日：1993-08-10

申请人： Brian D. McMinn ,  Robert H. Perlman ,  Prem Sobel

发明人： Brian D. McMinn ,  Robert H. Perlman ,  Prem Sobel

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/315 ,  G06F9/312

CPC分类号： G06F9/30094 ,  G06F9/30101

摘要： A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.

摘要翻译： 用于收集多个操作的布尔条件的处理器包括条件收集寄存器，其可以被并行地写入和读取，串行地写入，并且单个位从左或右移位到其中，并且处理器指令解码器解码一个操作数 寄存器地址作为条件收集寄存器的读取地址，三个操作数寄存器地址作为所述条件收集寄存器的写入地址。