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1.发明授权Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right 失效具有解码器的解码器，用于解码未修改的指令集，用于寻址寄存器并行读或写，或者从左或右顺序移位
公开(公告)号：US5327571A
公开(公告)日：1994-07-05
申请号：US104398
申请日：1993-08-10
申请人： Brian D. McMinn , Robert H. Perlman , Prem Sobel
发明人： Brian D. McMinn , Robert H. Perlman , Prem Sobel
CPC分类号： G06F9/30094 , G06F9/30101
摘要： A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.
摘要翻译： 用于收集多个操作的布尔条件的处理器包括条件收集寄存器，其可以被并行地写入和读取，串行地写入，并且单个位从左或右移位到其中，并且处理器指令解码器解码一个操作数 寄存器地址作为条件收集寄存器的读取地址，三个操作数寄存器地址作为所述条件收集寄存器的写入地址。
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公开(公告)号：US5053631A
公开(公告)日：1991-10-01
申请号：US503817
申请日：1990-04-02
申请人： Robert M. Perlman , Prem Sobel , Brian D. McMinn , Robert C. Thaden , Glenn A. Tamura , Thomas W. Lynch , Raju Vesgesna
发明人： Robert M. Perlman , Prem Sobel , Brian D. McMinn , Robert C. Thaden , Glenn A. Tamura , Thomas W. Lynch , Raju Vesgesna
CPC分类号： G06F7/483 , G06F2207/3884
摘要： A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.
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3.发明授权Parameterized random data generator providing a sequence of bytes with uniform statistical distribution 有权参数化随机数据生成器提供具有统一统计分布的字节序列公开(公告)号：US08995659B2
公开(公告)日：2015-03-31
申请号：US13914412
申请日：2013-06-10
申请人： Prem Sobel
发明人： Prem Sobel
CPC分类号： H04L9/0869 , H04L9/0662
摘要： A random data generator, a method, and a non-transitory machine-readable medium each operate a plurality of random number generators. Each random number generator is coupled to receive inputs comprising seed numbers, and generates an output stream of n-bit numbers. A bit-swap module receives each n-bit number and reorders the bits of the n-bit number to provide a reordered n-bit number. A byte select circuit selects a byte from the reordered n-bit number and provides a selected byte as an output to the random data stream.
摘要翻译： 随机数据生成器，方法和非暂时机器可读介质各自操作多个随机数生成器。 每个随机数发生器被耦合以接收包括种子号的输入，并且产生n位数的输出流。 位交换模块接收每个n位数，并重新排列n位数的位以提供重新排序的n位数。 字节选择电路从重新排序的n位数字中选择一个字节，并将所选字节提供给随机数据流的输出。
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4.发明申请PARAMETERIZED RANDOM DATA GENERATOR PROVIDING A SEQUENCE OF BYTES WITH UNIFORM STATISTICAL DISTRIBUTION 有权参数化随机数据生成器提供具有均匀统计分配的字节序列公开(公告)号：US20140362986A1
公开(公告)日：2014-12-11
申请号：US13914412
申请日：2013-06-10
申请人： Prem Sobel
发明人： Prem Sobel
IPC分类号： H04L9/08
CPC分类号： H04L9/0869 , H04L9/0662
摘要： A random data generator, a method, and a non-transitory machine-readable medium each operate a plurality of random number generators. Each random number generator is coupled to receive inputs comprising seed numbers, and generates an output stream of n-bit numbers. A bit-swap module receives each n-bit number and reorders the bits of the n-bit number to provide a reordered n-bit number. A byte select circuit selects a byte from the reordered n-bit number and provides a selected byte as an output to the random data stream.
摘要翻译： 随机数据生成器，方法和非暂时机器可读介质各自操作多个随机数生成器。 每个随机数发生器被耦合以接收包括种子号的输入，并且产生n位数的输出流。 位交换模块接收每个n位数，并重新排列n位数的位以提供重新排序的n位数。 字节选择电路从重新排序的n位数字中选择一个字节，并将所选字节提供给随机数据流的输出。
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公开(公告)号：US5128888A
公开(公告)日：1992-07-07
申请号：US504127
申请日：1990-04-02
申请人： Glenn A. Tamura , Prem Sobel
发明人： Glenn A. Tamura , Prem Sobel
CPC分类号： G06F7/483 , G06F2207/3884
摘要： An arithmetic logic unit includes structure for calculating in at least two stages, this structure including substructure for calculating in each of the at least two stages at least partially at the same time and substructure for ensuring the substructure for calculating in each of the at least two stages performs only one calculation at a time. Accumulators that work with pipe stages of a floating point unit may form all of part of the calculating structure. A method of performing calculations includes the steps of separating the calculations into at least two stages and separately accumulating the results of the stages using at least two accumulators, one each accumulator for each calculation at each of the at least two stages.
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