公开(公告)号：US20210117358A1

公开(公告)日：2021-04-22

申请号：US16803396

申请日：2020-02-27

申请人： Brian J. LePage ,  Carl R. Crandall

发明人： Brian J. LePage ,  Carl R. Crandall

IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F9/455 ,  H04L29/06

摘要： A computing system includes a computer executing an emulated operating system, the emulated operating system including a multichannel control unit; a plurality of virtual drives accessible to the emulated operating system; and a communication channel, the communication channel connecting the multichannel control unit and the virtual drives through one or more virtual channels. The multichannel control unit sends a first data access request to a virtual drive through the first virtual channel of the communication channel, the multichannel control unit sends a second data access request to a virtual drive through the second virtual channel of the communication channel.

公开(公告)号：US20210117357A1

公开(公告)日：2021-04-22

申请号：US16658269

申请日：2019-10-21

申请人： Brian J. LePage ,  Carl R. Crandall

发明人： Brian J. LePage ,  Carl R. Crandall

IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F9/455 ,  H04L29/06

摘要： A computing system includes a computer executing an emulated operating system, the emulated operating system including a multichannel control unit; a plurality of virtual drives accessible to the emulated operating system; and a communication channel, the communication channel connecting the multichannel control unit and the virtual drives through one or more virtual channels. The multichannel control unit sends a first data access request to a virtual drive through the first virtual channel of the communication channel, the multichannel control unit sends a second data access request to a virtual drive through the second virtual channel of the communication channel.

公开(公告)号：US20100211714A1

公开(公告)日：2010-08-19

申请号：US12371055

申请日：2009-02-13

申请人： Brian J. LePage

发明人： Brian J. LePage

IPC分类号： G06F13/372

CPC分类号： G06F13/1626

摘要： Transferring data between system memory and input/output busses involves determining, via a request buffer, a memory-mapped, input/output (I/O) read request targeted for a first-in-first-out (FIFO) I/O device. The read request is targeted to a request address in a prefetchable memory space corresponding to the I/O device. It is determined whether the request address corresponds to an expected address in the prefetchable memory space. The expected address is determined based on one or more previous read requests targeted to the prefetchable memory space. The read request is reordered in the request buffer if the request address does not correspond to the expected address. The read request is fulfilled if the address corresponds to the expected address.

摘要翻译： 在系统存储器和输入/输出总线之间传送数据涉及通过请求缓冲器确定针对先进先出（FIFO）I / O设备的存储器映射，输入/输出（I / O）读取请求 。 读取请求针对与I / O设备相对应的可预取存储器空间中的请求地址。 确定请求地址是否对应于可预取存储空间中的预期地址。 预期地址基于针对可预取存储器空间的一个或多个先前读取请求来确定。 如果请求地址与预期地址不对应，则请求缓冲区中的读请求被重新排序。 如果地址对应于预期地址，则读请求被满足。