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公开(公告)号：US08527808B2
公开(公告)日：2013-09-03
申请号：US13356054
申请日：2012-01-23
申请人： Brian Kelly , Michael J. Kasper
发明人： Brian Kelly , Michael J. Kasper
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , G06F11/2025 , G06F11/2028 , G06F11/2038 , G06F11/2043
摘要： In accordance with various aspects of the disclosure, a method and apparatus are disclosed that includes aspects of monitoring a first processor of a computer by a monitoring module for a first processor instability; determining if the first processor is stable based on the monitored first processor instability; routing operational priority to a second processor of the computer through a multiplexer module if the first processor is determined not to be stable, wherein a first interface of the first processor and a second interface of the second processor are in communication with the multiplexer module and wherein the first processor and the second processor are in communication by a processor interconnect; and operating the computer using the second processor.
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公开(公告)号：US20120124416A1
公开(公告)日：2012-05-17
申请号：US13356054
申请日：2012-01-23
申请人： Brian KELLY , Michael J. Kasper
发明人： Brian KELLY , Michael J. Kasper
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , G06F11/2025 , G06F11/2028 , G06F11/2038 , G06F11/2043
摘要： In accordance with various aspects of the disclosure, a method and apparatus are disclosed that includes aspects of monitoring a first processor of a computer by a monitoring module for a first processor instability; determining if the first processor is stable based on the monitored first processor instability; routing operational priority to a second processor of the computer through a multiplexer module if the first processor is determined not to be stable, wherein a first interface of the first processor and a second interface of the second processor are in communication with the multiplexer module and wherein the first processor and the second processor are in communication by a processor interconnect; and operating the computer using the second processor.
摘要翻译： 根据本公开的各个方面，公开了一种方法和装置，其包括通过用于第一处理器不稳定性的监视模块监视计算机的第一处理器的方面; 基于所监测的第一处理器不稳定性确定第一处理器是否稳定; 如果第一处理器被确定为不稳定，则通过多路复用器模块将操作优先级路由到计算机的第二处理器，其中第一处理器的第一接口和第二处理器的第二接口与多路复用器模块通信，并且其中 第一处理器和第二处理器通过处理器互连进行通信; 并使用第二处理器操作计算机。
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公开(公告)号：US07128197B2
公开(公告)日：2006-10-31
申请号：US11160078
申请日：2005-06-08
IPC分类号： B65G1/00
CPC分类号： B65G47/261 , B65G43/08
摘要： A sortation system and method includes providing a sorter assembly and a slug-building assembly. Product is received by the sorter assembly and sorted to a series of sortation lanes. The slug-building assembly includes a plurality of supply lines supplying product for sorting by the sorter assembly. At least one of the supply lines includes an accumulation conveyor and a slug conveyor. Product is accumulated in slug portions at the accumulation conveyor. Slug portions are combined into product slugs at the slug conveyor. Product slugs are discharged from the slug conveyor for sorting by the sorter assembly.
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公开(公告)号：US06923307B2
公开(公告)日：2005-08-02
申请号：US10065789
申请日：2002-11-19
CPC分类号： B65G47/261 , B65G43/08
摘要： A sortation system and method includes providing a sorter assembly and a slug-building assembly. Product is received by the sorter assembly and sorted to a series of sortation lanes. The slug-building assembly includes a plurality of supply lines supplying product for sorting by the sorter assembly. At least one of the supply lines includes an accumulation conveyor and a slug conveyor. Product is accumulated in slug portions at the accumulation conveyor. Slug portions are combined into product slugs at the slug conveyor. Product slugs are discharged from the slug conveyor for sorting by the sorter assembly.
摘要翻译： 排序系统和方法包括提供分拣机组件和s块构造组件。 产品由分拣机组件接收并分拣到一系列分拣车道。 桩部件组件包括多个供给线，供给由分拣机组件进行分拣的产品。 供应管线中的至少一个包括堆积输送机和排料输送机。 产品积聚在堆积输送机的块状部分。 块状部分在块状输送机上组合成产品块。 产品块从排料输送机排出，由分拣机组件分拣。
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公开(公告)号：US09659272B2
公开(公告)日：2017-05-23
申请号：US13976327
申请日：2012-04-05
申请人： Thomas A. Birch , Michael J. Kasper
发明人： Thomas A. Birch , Michael J. Kasper
CPC分类号： G06Q10/087
摘要： A method and apparatus for attending to a supply of product at a position on a store shelf involves receiving an electronic image of the position on a store shelf and comparing the electronic image to a previous electronic image of the position on the store shelf. Depending of the difference, if any, between the two images, generating an indication to attend to the supply of product at the position on the store shelf.
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公开(公告)号：US06229811B1
公开(公告)日：2001-05-08
申请号：US09556581
申请日：2000-04-24
IPC分类号： H04L1228
CPC分类号： H04L49/351 , H04L49/40
摘要： The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
摘要翻译： 本发明涉及包括耦合到所述第一和第二电路的第一电路，第二电路和逻辑电路的方法和架构。 第一段通常包括被配置为以多个速度中的一个速度操作的第一中继器核和第一端口。 第二段通常包括被配置为以多个速度中的一个速度操作的第二中继器核和第二端口。 逻辑电路可以被配置为将第一和第二端口中的每一个耦合到第一或第二中继器核心。
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公开(公告)号：US6055241A
公开(公告)日：2000-04-25
申请号：US970059
申请日：1997-11-13
IPC分类号： H04L12/56 , H04L12/413
CPC分类号： H04L49/351 , H04L49/40
摘要： The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
摘要翻译： 本发明涉及包括耦合到所述第一和第二电路的第一电路，第二电路和逻辑电路的方法和架构。 第一段通常包括被配置为以多个速度中的一个速度操作的第一中继器核和第一端口。 第二段通常包括被配置为以多个速度中的一个速度操作的第二中继器核和第二端口。 逻辑电路可以被配置为将第一和第二端口中的每一个耦合到第一或第二中继器核心。
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