公开(公告)号：US06505317B1

公开(公告)日：2003-01-07

申请号：US09534839

申请日：2000-03-24

申请人： Brian L. Smith ,  James C. Lewis ,  David Broniarczyk

发明人： Brian L. Smith ,  James C. Lewis ,  David Broniarczyk

IPC分类号： G06F1100

CPC分类号： G01R31/318505 ,  G06F11/221

摘要： A system and method for testing signal interconnections using built-in self test (BIST). BIST functionality is designed into the various chips of a computer system. These chips include a transmit unit, a receive unit, a control logic unit, and a central logic unit. A control logic unit associated with a signal block (i.e. a group of signals) configures the signal block for either testing or normal operation. The central logic unit performs test pattern generation for all signal blocks on a given chip. Chips may act as either a master or slave chip during testing. When acting as a master chip, the transmit unit of the chip drives test patterns onto one or more signal lines. The receive unit of the slave chip returns a corresponding test pattern to the master chip after receiving the transmitted test pattern. A receive unit on the master chip receives the corresponding test patterns and performs verification. All tests occur at the operational clock speed of the computer system. A master and a slave chip need not be mounted upon the same circuit board, allowing for tests through connectors within a computer system.

摘要翻译： 使用内置自检（BIST）测试信号互连的系统和方法。 BIST功能被设计到计算机系统的各种芯片中。 这些芯片包括发送单元，接收单元，控制逻辑单元和中央逻辑单元。 与信号块（即，一组信号）相关联的控制逻辑单元配置用于测试或正常操作的信号块。 中央逻辑单元为给定芯片上的所有信号块执行测试模式生成。 在测试期间，芯片可以作为主芯片或从芯片。 当作为主芯片时，芯片的发送单元将测试模式驱动到一条或多条信号线上。 子芯片的接收单元在接收到发送的测试图案之后，将相应的测试图案返回给主芯片。 主芯片上的接收单元接收相应的测试模式并进行验证。 所有测试都以计算机系统的运行时钟速度发生。 主芯片和从芯片不需要安装在同一个电路板上，允许通过计算机系统内的连接器进行测试。

公开(公告)号：US5978874A

公开(公告)日：1999-11-02

申请号：US673038

申请日：1996-07-01

申请人： Ashok Singhal ,  Bjorn Liencres ,  Jeff Price ,  Frederick M. Cerauskis ,  David Broniarczyk ,  Gerald Cheung ,  Erik Hagersten ,  Nalini Agarwal

发明人： Ashok Singhal ,  Bjorn Liencres ,  Jeff Price ,  Frederick M. Cerauskis ,  David Broniarczyk ,  Gerald Cheung ,  Erik Hagersten ,  Nalini Agarwal

IPC分类号： G06F12/08 ,  G06F13/368 ,  G06F13/00

CPC分类号： G06F13/368 ,  G06F12/0831

摘要： Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.

摘要翻译： 在具有一个或多个这样的总线的计算机系统的分离事务监听总线上实现侦听。 电路板包括CPU或其他设备和/或分布式存储器，数据输入/输出缓冲器，包括请求标签队列，相干输入队列（“CIQ”）和地址控制器的队列，实现地址总线仲裁插入到一个或多个拆分事务监听 总线系统 所有设备在地址总线上窥探，了解所标识的行是否拥有或共享，并发出适当的拥有/共享信号。 接收忽略信号阻止事务的CIQ加载，直到重新加载事务并忽略忽略。 所请求的内存线的所有权在请求时立即转移。 被排除的请求排队，使得地址总线上的状态事务在逻辑上发生，而不依赖于请求。 对相同数据的后续请求被标记为成为所有者请求者的责任。 后续请求者的活动不会暂停等待授予并完成较早的请求事务。 处理器级缓存在收到交易数据后更改状态。 单个复用仲裁总线承载地址总线和数据总线请求事务，这些事务的长度分别为两个周期。

公开(公告)号：US5911052A

公开(公告)日：1999-06-08

申请号：US673967

申请日：1996-07-01

申请人： Ashok Singhal ,  Bjorn Liencres ,  Jeff Price ,  Frederick M. Cerauskis ,  David Broniarczyk ,  Gerald Cheung ,  Erik Hagersten ,  Nalini Agarwal

发明人： Ashok Singhal ,  Bjorn Liencres ,  Jeff Price ,  Frederick M. Cerauskis ,  David Broniarczyk ,  Gerald Cheung ,  Erik Hagersten ,  Nalini Agarwal

IPC分类号： G06F12/08 ,  G06F13/368 ,  G06F13/00

CPC分类号： G06F13/368 ,  G06F12/0831

摘要： A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.

摘要翻译： 分组交易监听总线协议和架构被提供用于具有一个或多个这样的总线的系统中。 电路板包括CPU或其他设备和/或分布式存储器，数据输入/输出缓冲器，包括请求标签队列，相干输入队列（“CIQ”）和地址控制器的队列，实现地址总线仲裁插入到一个或多个拆分事务监听 总线系统 所有设备在地址总线上窥探，了解所标识的行是否拥有或共享，并发出适当的拥有/共享信号。 接收忽略信号阻止事务的CIQ加载，直到重新加载事务并忽略忽略。 所请求的内存线的所有权在请求时立即转移。 被排除的请求排队，使得地址总线上的状态事务在逻辑上发生，而不依赖于请求。 对相同数据的后续请求被标记为成为所有者请求者的责任。 后续请求者的活动不会暂停等待授予并完成较早的请求事务。 处理器级缓存在收到交易数据后更改状态。 单个复用仲裁总线承载地址总线和数据总线请求事务，这些事务的长度分别为两个周期。