公开(公告)号：USRE40877E1

公开(公告)日：2009-08-18

申请号：US12171191

申请日：2008-07-10

申请人： Ashok Singhal ,  David J. Broniarczyk ,  George R. Cameron ,  Jeff A. Price

发明人： Ashok Singhal ,  David J. Broniarczyk ,  George R. Cameron ,  Jeff A. Price

IPC分类号： G06F15/167

CPC分类号： G06F12/0813 ,  G06F12/0831

摘要： A method is provided for communicating data in an interconnect system comprising a plurality of nodes. In one aspect, the method includes: issuing a command packet from a first node, the command packet comprising a respective header quadword and at least one respective data quadword for conveying a command to a second node, wherein the command is selected from a group comprising a direct memory access (DMA) command, an administrative write command, a memory copy write command, and a built in self test (BIST) command; receiving the command packet at the second node; issuing an acknowledgement packet from the second node, the acknowledgement packet comprising a respective header quadword for conveying an acknowledgement that the command packet has been received at the second node.

摘要翻译： 提供一种用于在包括多个节点的互连系统中传送数据的方法。 一方面，该方法包括：从第一节点发出命令分组，该命令分组包括相应的首标四字和至少一个相应的数据四字，用于将命令传送到第二节点，其中该命令选自包括 直接存储器访问（DMA）命令，管理写入命令，存储器复制写入命令和内置自检（BIST）命令; 在第二节点接收命令包; 从所述第二节点发出确认分组，所述确认分组包括相应的报头四字，用于传送在所述第二节点处已经接收到所述命令分组的确认。

公开(公告)号：US07502903B2

公开(公告)日：2009-03-10

申请号：US11269399

申请日：2005-11-07

申请人： Sushil Thomas ,  Ashok Singhal

发明人： Sushil Thomas ,  Ashok Singhal

IPC分类号： G06F12/02

CPC分类号： G06F3/0647 ,  G06F3/0607 ,  G06F3/0631 ,  G06F3/0689

摘要： A method is provided for a data storage system to move data from a source logical disk (LD) region to a target LD region while the data storage system remains online to a host. The method includes determining if a region move will create excessive load so the data storage system appears offline to the host. If not, the method includes causing writes to the source LD region to be mirrored to the target LD region, causing data in the source LD region to be copied to the target LD region, blocking reads and writes to the data storage system, and flushing dirty cache in the data storage system. If flushing the dirty cache is fast so the data storage system appears online to the host, the method includes updating mappings of the virtual volume to the LD regions and resuming the reads and writes to the data storage system.

摘要翻译： 提供了一种用于数据存储系统将数据从源逻辑磁盘（LD）区域移动到目标LD区域的方法，同时数据存储系统保持在主机上。 该方法包括确定区域移动是否会产生过大的负载，从而使数据存储系统对主机显示脱机。 如果不是，则该方法包括使源LD区域的写入被映射到目标LD区域，使得源LD区域中的数据被复制到目标LD区域，阻止对数据存储系统的读取和写入以及冲洗 脏缓存在数据存储系统中。 如果刷新脏缓存是快速的，所以数据存储系统在主机上出现，该方法包括将虚拟卷的映射更新到LD区域，并恢复对数据存储系统的读写操作。

公开(公告)号：US06578033B1

公开(公告)日：2003-06-10

申请号：US09597863

申请日：2000-06-20

申请人： Ashok Singhal ,  Erik Hagersten

发明人： Ashok Singhal ,  Erik Hagersten

IPC分类号： G06F1730

CPC分类号： G06F9/52 ,  Y10S707/99938

摘要： A probabilistic queue lock divides requesters for a lock into at least three sets. In one embodiment, the requesters are divided into the owner of the lock, the first waiting contender, and the other waiting contenders. The first waiting contender is made probabilistically more likely to obtain the lock by having it spin faster than the other waiting contenders. Because the other waiting contenders spin more slowly, the first waiting contender is more likely to be able to observe the free lock and acquire it before the other waiting contenders notice that it is free. The first of the other waiting contenders that determines that the previous first waiting contender has acquired the lock is promoted to be the new first waiting contender and begins spinning fast. Because only the first waiting contender is spinning fast on the lock, it is probable that only the first waiting contender will attempt to acquire the lock when it becomes available.

摘要翻译： 概率队列锁定将请求者锁定至少三组。 在一个实施例中，请求者被分为锁的所有者，第一等待竞争者和其他等待竞争者。 第一个等待竞争者的概率比其他等待竞争者更容易获得锁。 由于其他等待竞争者的旋转速度较慢，第一个等待竞争者更有可能在其他等待竞争者注意到自由之前观察到免费锁定并获得锁定。 第一个等待竞争者的第一个等待竞争者，确定先前的第一个等待竞争者已经获得锁被提升为新的第一个等待竞争者，并开始快速旋转。 因为只有第一个等待竞争者在锁上快速旋转，所以只有第一个等待竞争者才有可能尝试获取锁。

公开(公告)号：US06574746B1

公开(公告)日：2003-06-03

申请号：US09347117

申请日：1999-07-02

申请人： Tayung Wong ,  Ashok Singhal ,  Clement Fang ,  John Carrillo ,  Han Y. Ko

发明人： Tayung Wong ,  Ashok Singhal ,  Clement Fang ,  John Carrillo ,  Han Y. Ko

IPC分类号： G06F1108

CPC分类号： G06F11/1012 ,  G06F11/102

摘要： A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.

摘要翻译： 一种用于在计算机存储器模块中存储纠错检查词的系统和方法。 检查存储在动态随机存取存储器（DRAM）芯片内的物理相邻位置的位被分配给不同的检查字。 通过以这种方式分配校验位以检查字，存储在物理上相邻的存储器位置中的两个或更多个校验位中的错误导致的多位软错误将作为单位错误出现到纠错子系统。 类似地，可以减少在相同检查字中发生的多位错误的可能性。

公开(公告)号：US5987549A

公开(公告)日：1999-11-16

申请号：US675286

申请日：1996-07-01

申请人： Erik Hagersten ,  Ashok Singhal

发明人： Erik Hagersten ,  Ashok Singhal

IPC分类号： G06F12/08 ,  G06F13/368 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F13/368

摘要： Low-latency distributed round-robin arbitration is used to grant requests for access to a shared resource such as a computer system bus. A plurality of circuit board cards that each include two devices such as CPUs, I/O units, and ram and an address controller plugs into an Address Bus in the bus system. Each address controller contains logic implementing the arbitration mechanism with a two-level hierarchy: a single top arbitrator and preferably four leaf arbitrators. Each address controller is coupled to two devices and the logical "OR" of their arbitration request is coupled via an Arbitration Bus to other address controllers on other boards. Each leaf arbitrator has four prioritized request in lines, each such line being coupled to a single address controller serviced by that leaf arbitrator. By default, each leaf arbitrator and the top arbitrator implement a prioritized algorithm. However a last winner ("LW") state is maintained at every arbitrator that overrides the default, to provide round-robin selection. Each leaf arbitrator arbitrates among the zero to four requests it sees, selects a winner and signals the top arbitrator that it has a device wishing access. At the top arbitrator, if the first leaf arbitrator last won a grant, it now has lowest grant priority, and a grant will go to the next highest leaf arbitrator having a device seeking access.

摘要翻译： 低延迟分布式循环仲裁用于授予访问共享资源（如计算机系统总线）的请求。 多个电路板卡每个包括诸如CPU，I / O单元和RAM的两个设备和地址控制器插入总线系统中的地址总线中。 每个地址控制器包含实现具有两级层次的仲裁机制的逻辑：单个顶级仲裁器，最好是四个叶子仲裁器。 每个地址控制器耦合到两个设备，并且其仲裁请求的逻辑“或”通过仲裁总线耦合到其他板上的其他地址控制器。 每个叶子仲裁器具有四个优先级的请求，每个这样的行被耦合到该叶子仲裁器所服务的单个地址控制器。 默认情况下，每个叶子仲裁器和顶级仲裁器实现优先级算法。 然而，每个仲裁员维护最后一个赢家（“LW”）状态，以覆盖默认值，以提供循环选择。 每个叶仲裁员在它看到的零到四个请求之间进行仲裁，选择一个获胜者，并向顶级仲裁员发出信号，指示它具有希望访问的设备。 在最高的仲裁员身上，如果第一个叶子仲裁员最后一次获得授权，那么它现在具有最低的授权优先权，而授权将转到具有寻求访问权限的设备的下一个最高的叶子仲裁员。

公开(公告)号：US5765196A

公开(公告)日：1998-06-09

申请号：US607364

申请日：1996-02-27

申请人： Bjorn O. Liencres ,  Ashok Singhal ,  David J. Broniarczyk

发明人： Bjorn O. Liencres ,  Ashok Singhal ,  David J. Broniarczyk

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/14

CPC分类号： G06F12/0804 ,  G06F12/0833

摘要： In a multiprocessor system having a shared memory, each central processor services copyback requests from other central processors. Each central processor has a writeback buffer along with a plurality of tag buffers and an associated snoop architecture for processing writeback and copyback commands. Each central processor includes a cache subsystem having a system interface, a main cache and an associated tag array. The system interface has an address controller and data controller, each having separate input and output queues for interfacing between the central processor and system control and data buses. The address controller includes a set of duplicate tags that mirror the tags associated with the main cache, and an auxiliary tag input buffer and auxiliary tag output buffer. The address controller has for each line in the output queue an associated pointer that indicates the location in the data controller where data is stored that is associated with output queued commands. In operation, the address controller processes inbound multiple copyback requests without requiring the central processor to access data from its associated main cache. The address controller utilizes the output queues in the address and data controller as well as the auxiliary tag buffers to store copyback data and tag information.

摘要翻译： 在具有共享存储器的多处理器系统中，每个中央处理器服务来自其他中央处理器的复制请求。 每个中央处理器具有回写缓冲器以及多个标签缓冲器以及相关联的窥探架构，用于处理写回和复制命令。 每个中央处理器包括具有系统接口，主缓存和相关标签阵列的缓存子系统。 系统接口具有一个地址控制器和数据控制器，每个都具有单独的输入和输出队列，用于中央处理器与系统控制和数据总线之间的接口。 地址控制器包括一组反映与主缓存相关联的标签的重复标签，以及辅助标签输入缓冲器和辅助标签输出缓冲器。 地址控制器对于输出队列中的每一行都有一个关联的指针，指示数据控制器中存储与输出排队命令相关联的数据的位置。 在操作中，地址控制器处理入站多个回拷请求，而不要求中央处理器从其相关联的主缓存访问数据。 地址控制器利用地址和数据控制器中的输出队列以及辅助标签缓冲器来存储副本数据和标签信息。

公开(公告)号：US07328743B2

公开(公告)日：2008-02-12

申请号：US11534542

申请日：2006-09-22

申请人： Alex Turta ,  Fred Wassmuth ,  Vijay Shrivastava ,  Ashok Singhal

发明人： Alex Turta ,  Fred Wassmuth ,  Vijay Shrivastava ,  Ashok Singhal

IPC分类号： E21B33/138 ,  E21B43/20 ,  E21B43/22 ,  E21B43/30

CPC分类号： E21B43/20 ,  E21B43/305 ,  E21B43/32

摘要： A modified toe-to-heel waterflooding (TTHW) process is provided for recovering oil from a reservoir in an underground formation. After establishing the conventional TTHW waterflood, the process includes placing a chemical blocking agent at the watered out producing toe portion of the horizontal leg of the production well to create a blockage in the producing toe portion and to create a new producing toe portion in an open portion of the horizontal leg adjacent the blockage through which most of the production takes place. Production is then continued through the new producing toe portion and the open portion of the horizontal leg of the production well. These blocking and producing steps can be continued to progressively block producing toe portions in a direction toward the vertical pilot portion of the production well.

摘要翻译： 提供了一种改进的脚趾到脚跟注水（TTHW）工艺，用于从地下地层的储层中回收油。 在建立传统的TTHW注水后，该方法包括将化学阻塞剂放置在生产井的水平腿的浇水生产脚趾部分，以在生产趾部产生堵塞，并在开口中产生新的生产趾部 靠近大多数生产发生的堵塞的水平腿的部分。 然后通过新生产的脚趾部分和生产井的水平腿的开口部分继续生产。 这些堵塞和制造步骤可以继续沿着朝向生产井的垂直先导部分的方向逐渐地阻止制造趾部。

公开(公告)号：US20050044174A1

公开(公告)日：2005-02-24

申请号：US10821729

申请日：2004-04-09

申请人： Anders Landin ,  Robert Cypher ,  Erik Hagersten ,  Ashok Singhal

发明人： Anders Landin ,  Robert Cypher ,  Erik Hagersten ,  Ashok Singhal

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F12/0831

摘要： A system may include a plurality of nodes coupled by an inter-node network. Each of the nodes includes several active devices, an interface to the inter-node network, and an address network coupling the active devices to the interface. An active device included in one of the nodes initiates a transaction by sending either a first type of address packet or a second type of address packet on the address network dependent on whether the active device is included in a multi-node system. The first type of address packet is sent if the active device is included in a multi-node system and is not snooped by other active devices in the same node as the active device. The second type of address packet, sent if the active device is included in a single node system, is snooped by other active devices in the same node as the active device.

摘要翻译： 系统可以包括由节点间网络耦合的多个节点。 每个节点包括若干活动设备，节点间网络的接口以及将活动设备耦合到接口的地址网络。 包括在其中一个节点中的活动设备通过在地址网络上发送第一类型的地址分组或第二类型的地址分组来发起交易，这取决于活动设备是否包括在多节点系统中。 如果活动设备包括在多节点系统中并且不与主动设备在同一节点中的其他活动设备进行窥探，则发送第一类地址分组。 如果活动设备包含在单个节点系统中，则发送的第二种类型的地址分组被与活动设备在同一节点中的其他活动设备进行探测。

公开(公告)号：US06658478B1

公开(公告)日：2003-12-02

申请号：US09633088

申请日：2000-08-04

申请人： Ashok Singhal ,  Jeffrey A. Price ,  David J. Broniarczyk ,  George C. Cameron

发明人： Ashok Singhal ,  Jeffrey A. Price ,  David J. Broniarczyk ,  George C. Cameron

IPC分类号： G06F1516

CPC分类号： H04L67/42 ,  G06F3/0601 ,  G06F2003/0692

摘要： A data storage system includes a plurality of nodes for providing access to a data storage facility. Each node has a computer-memory complex to provide general purpose computing for the node, a node controller to control data transfers through the respective node, and a cluster memory to buffer data for the data transfers. A plurality of communication paths interconnect the nodes, with a separate communication path provided for each two nodes of the data storage system.

摘要翻译： 数据存储系统包括用于提供对数据存储设施的访问的多个节点。 每个节点都有一个计算机内存复杂系统，为节点提供通用计算，一个节点控制器来控制通过各个节点的数据传输，以及一个集群存储器来缓冲数据传输的数据。 多个通信路径使节点互连，为数据存储系统的每两个节点提供单独的通信路径。

公开(公告)号：US06272602B1

公开(公告)日：2001-08-07

申请号：US09265233

申请日：1999-03-08

申请人： Ashok Singhal ,  Alan Yamauchi ,  Gary Lauterbach

发明人： Ashok Singhal ,  Alan Yamauchi ,  Gary Lauterbach

IPC分类号： G06F1210

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A pending tag system and method to maintain data coherence in a processing node during pending transactions in a transaction pipeline. A pending tag storage unit may be coupled to a cache controller and configured to store pending tags each indicative of a coherence state for a data line corresponding to a pending transaction within the transaction pipeline. The pending tag storage unit includes a total amount of storage which is substantially less than an amount required to store tags contained in the full tag array for the cache memory. When a pending tag exists in the pending tag storage unit, the coherence state of the corresponding data line within the cache memory is dictated by the pending tag for snoop operations. Accordingly, data coherence is maintained during the period when transactions are pending, e.g., not yet presented to a processor and cache. When a pending transaction is completed, the coherence state of the corresponding data line as indicated by the fill tag array may be overwritten by the coherence state as indicated by the pending tag and the pending tag may deleted from the pending tag storage.

摘要翻译： 待处理的标签系统和方法，用于在事务流水线中的待处理事务期间维护处理节点中的数据一致性。 挂起的标签存储单元可以耦合到高速缓存控制器，并且被配置为存储每个指示对应于事务流水线内的待处理事务的数据线的相干状态的挂起标签。 待处理标签存储单元包括总量大大小于存储包含在高速缓存存储器的完整标签阵列中的标签所需的量的存储量。 当挂起的标签存储单元中存在未决的标签时，高速缓冲存储器内相应数据线的相干状态由窥探操作的挂起标签决定。 因此，在事务处于待处理期间，例如尚未呈现给处理器和高速缓存的期间，维持数据一致性。 当待处理的事务完成时，由填充标签阵列指示的对应数据行的相干状态可以由挂起标签所指示的相干状态覆盖，并且待决标签可以从挂起的标签存储中删除。