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公开(公告)号：US5878229A
公开(公告)日：1999-03-02
申请号：US968677
申请日：1997-11-12
CPC分类号： H04L12/44
摘要： A sequence in which two or more of the data units enter the network node, via a specific one of the multiple ports, is recorded. And, the two or more of the data units are transmitted from the network node according to the recorded sequence. The method and system achieve the recording of sequence via the following. In response to an insertion of one of the two or more data units into a specific one of the multiple processor subsystems, the specific one of the multiple processor subsystems is associated with a specific one of the multiple ports by which the one of the two or more data units entered the network node, and any other of the multiple processor subsystems that are currently processing on any other of the two or more data units that entered the network node through the specific one of the multiple ports is noted. Thereafter, any request to transmit by the specific one of the multiple processors is honored if it is determined that the data unit with the requesting processor is next according to the recorded sequence. The data unit is determined to be next in sequence if all of the multiple processors, that were processing on other data units which entered through the specific one of the multiple ports, have completed processing.
摘要翻译： 记录两个或多个数据单元经由多个端口中的特定一个进入网络节点的序列。 并且，根据记录的顺序，从网络节点发送两个或更多个数据单元。 该方法和系统通过以下方式实现序列的记录。 响应于将两个或多个数据单元中的一个数据单元中的一个插入到多个处理器子系统中的特定的一个中，多个处理器子系统中的特定一个与多个端口中的特定的一个相关联，通过该特定的一个或多个 记录更多的数据单元进入网络节点，并且注意当前正在通过多个端口中的特定一个进入网络节点的两个或多个数据单元中的任何其他数据单元上处理的多个处理器子系统中的任何其他处理器子系统。 此后，如果根据所记录的序列确定与请求处理器的数据单元是下一个，则可以保证由多个处理器中的特定一个处理器发送的任何请求。 如果对通过多个端口中的特定一个进入的其他数据单元进行处理的所有多个处理器已经完成了处理，则数据单元被确定为顺序。
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公开(公告)号：US06178462B1
公开(公告)日：2001-01-23
申请号：US08977230
申请日：1997-11-24
申请人： Brian M. Bass , Dennis Albert Doidge , Edward Hau-chun Ku , Scott J. Lemke , Joseph M. Rash , Loren Blair Reiss
发明人： Brian M. Bass , Dennis Albert Doidge , Edward Hau-chun Ku , Scott J. Lemke , Joseph M. Rash , Loren Blair Reiss
IPC分类号： G06F1516
CPC分类号： G06F13/385
摘要： A system for coupling a local area network to a wide area network utilizes a PCI (Peripheral Component Interface) bus to couple a PCI interface to a PCI network interface card, which is coupled to the wide area network. The wide area network could be an asynchronous transfer mode network or a high bandwidth ethernet. If the PCI network interface card operates as a PCI master, then the PCI interface will operate as a PCI slave. If the PCI network interface card operates as a PCI slave, then the PCI interface of the invention will operate as a PCI master.
摘要翻译： 用于将局域网连接到广域网的系统利用PCI（外围组件接口）总线将PCI接口耦合到耦合到广域网的PCI网络接口卡。 广域网可以是异步传输模式网络或高带宽以太网。 如果PCI网络接口卡作为PCI主机运行，则PCI接口将作为PCI从站运行。 如果PCI网络接口卡作为PCI从设备操作，则本发明的PCI接口将作为PCI主机操作。
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3.发明授权Simultaneous cut through and store-and-forward frame support in a network device 失效在网络设备中同时切割和存储转发帧支持
公开(公告)号：US6144668A
公开(公告)日：2000-11-07
申请号：US979043
申请日：1997-11-26
申请人： Brian M. Bass , Douglas Ray Henderson , Edward Hau-chun Ku , Scott J. Lemke , Joseph M. Rash , Loren Blair Reiss , Thomas Eric Ryle
发明人： Brian M. Bass , Douglas Ray Henderson , Edward Hau-chun Ku , Scott J. Lemke , Joseph M. Rash , Loren Blair Reiss , Thomas Eric Ryle
CPC分类号： H04L45/00 , H04L49/251 , H04L49/351 , H04L49/602
摘要： A method and system are provided for enabling simultaneous cut-through and store-and-forward transmission of frames in high speed network devices. A Buffer Parameter Vector chains multiple frame buffers together. Frame Parameter Vectors created for each unique version of a frame are used to manage frames as they flow through the network device. Cut-through/store-and-forward decision logic determines whether frames can be transmitted by cut-through or store-and-forward. Multiple unique frames or copies of a frame that are to be transmitted store-and-forward have their Frame Parameter Vectors chained together by pointers. The cut-through/store-and-forward decision logic steps through the chain of Frame Parameter Vectors resulting in the frames associated with each Frame Parameter Vector being transmitted.
摘要翻译： 提供了一种方法和系统，用于实现高速网络设备中的帧的同步切换和存储转发传输。 缓冲区参数向量将多个帧缓冲区链接在一起。 为每个唯一版本的帧创建的帧参数向量用于在帧流经过网络设备时管理帧。 直通/存储转发决策逻辑确定帧是否可以通过直通或存储转发传输。 要发送的多个唯一帧或帧副本存储和转发使其参数向量通过指针链接在一起。 切入/存储和转发决策逻辑逐步通过帧参数向量链，导致与正在发送的每个帧参数向量相关联的帧。
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公开(公告)号：US06272134B1
公开(公告)日：2001-08-07
申请号：US08975231
申请日：1997-11-20
申请人： Brian M. Bass , Douglas R. Henderson , Edward Hau-chun Ku , Scott J. Lemke , Joseph M. Rash , Loren Blair Reiss , Thomas Eric Ryle
发明人： Brian M. Bass , Douglas R. Henderson , Edward Hau-chun Ku , Scott J. Lemke , Joseph M. Rash , Loren Blair Reiss , Thomas Eric Ryle
IPC分类号： H04L1256
CPC分类号： H04L12/18
摘要： A method and system are provided for increasing processing efficiency associated with data frames transiting a network node having multiple ports. The method and system accomplish their objects via the following. A data frame having a header and data is received. An associated pointer for at least one portion of the received data frame is provided. The associated pointer is provided by segmenting each received data frame into parts, and associating with each segmented part a pointer. Thereafter, a portion of the received data frame is modified independent of other portions of the received data frame via utilization of given one or more of the associated pointers. Additionally, one or more copies of a portion (which can include the whole) of the received data frame is constructed by recalling each segmented part associated with one or more selected ones of the associated pointers. Furthermore, a determination is made as to whether the received header indicates unicast or multicast. In response to this determination, a number of data frames are constructed commensurate with protocols and destination addresses of one or more network nodes to which the constructed number of data frames is to be transmitted. The constructed data frames are transmitted from the node.
摘要翻译： 提供了一种用于提高与跨过具有多个端口的网络节点的数据帧相关联的处理效率的方法和系统。 该方法和系统通过以下方式完成其对象。 接收具有报头和数据的数据帧。 提供了用于接收的数据帧的至少一部分的相关联的指针。 通过将每个接收到的数据帧分割成多个部分并且与每个分割部分相关联的指针来提供相关联的指针。 此后，接收到的数据帧的一部分通过使用给定的一个或多个相关联的指针而被独立于接收到的数据帧的其他部分进行修改。 此外，通过调用与相关联的指针中的一个或多个所选择的相关联的指针相关联的每个分段部分来构造所接收的数据帧的一部分（其可以包括整体）的一个或多个副本。 此外，确定所接收的报头是指示单播还是组播。 响应于该确定，构造与要被发送所构造的数据帧数量的一个或多个网络节点的协议和目的地地址相对应的多个数据帧。 构建的数据帧从节点传输。
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公开(公告)号：US6052375A
公开(公告)日：2000-04-18
申请号：US980090
申请日：1997-11-26
申请人： Brian M. Bass , Jim P. Ervin , Douglas Ray Henderson , Edward Hau-chun Ku , Joseph Kinman Lee , Scott J. Lemke , Joseph M. Rash , Loren Blair Reiss
发明人： Brian M. Bass , Jim P. Ervin , Douglas Ray Henderson , Edward Hau-chun Ku , Joseph Kinman Lee , Scott J. Lemke , Joseph M. Rash , Loren Blair Reiss
IPC分类号： H04L12/56
CPC分类号： H04L47/24 , H04L12/5693 , H04L47/10 , H04L47/22 , H04L47/39 , H04L47/522 , H04L47/527 , H04L47/6225 , H04L49/90
摘要： A method and system are provided for traffic shaping and bandwidth scaling in a high speed internetworking device. A slot time wheel mechanism is provided for traffic rate control and a credit/debit mechanism is provided for traffic shaping and scaling. The high speed traffic scaler and shaper incorporates a programmable slot time wheel, a traffic scaler state machine, a traffic shaper parameter table and a traffic scaler processor. The traffic scaler processor incorporates a traffic queue allocation manager, a queue priority arbiter, a port enable selector, a port priority arbiter and a DMA channel arbiter. The traffic queue allocation manager and the queue priority, port priority and DMA channel arbiters are each controlled by a corresponding state machine. The parameters in the traffic shaper parameter table are dynamically updated for each logical queue and are used to enable the credit/debit mechanism.
摘要翻译： 提供了一种用于高速互联网络设备中的流量整形和带宽缩放的方法和系统。 提供了时隙时间轮机制，用于通信速率控制，并提供信用/借记机制用于流量整形和缩放。 高速流量缩放器和整形器结合了可编程时隙时间轮，流量缩放器状态机，流量整形器参数表和流量缩放器处理器。 流量缩放器处理器包括流量队列分配管理器，队列优先仲裁器，端口使能选择器，端口优先仲裁器和DMA通道仲裁器。 流量队列分配管理器和队列优先级，端口优先级和DMA通道仲裁器均由相应的状态机控制。 流量整形器参数表中的参数为每个逻辑队列动态更新，并用于启用信用/借记机制。
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公开(公告)号：US08131967B2
公开(公告)日：2012-03-06
申请号：US11622445
申请日：2007-01-11
CPC分类号： G06F13/4059
摘要： An interface system is disclosed. In one embodiment, the system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the system and method disclosed herein, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.
摘要翻译： 公开了一种接口系统。 在一个实施例中，该系统包括缓冲器，该缓冲器从第一时钟域中的源接收数据，并将要由目的地读取的数据存储在第二时钟域中，其中缓冲器在第一时钟域和第二时钟 域; 一个写入指针，指向由源写入的数据; 以及指向目的地读取的数据的读指针。 根据本文公开的系统和方法，写指针和读指针用于使数据能够异步地从第一时钟域发送到第二时钟域。
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公开(公告)号：US07966435B2
公开(公告)日：2011-06-21
申请号：US12105449
申请日：2008-04-18
CPC分类号： G06F13/4059
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.
摘要翻译： 公开了一种体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构，包括用于接口系统的设计结构。 该系统包括缓冲器，其从第一时钟域中的源接收数据，并将要由目的地读取的数据存储在第二时钟域中，其中缓冲器在第一时钟域和第二时钟域两者中起作用; 一个写入指针，指向由源写入的数据; 以及指向目的地读取的数据的读指针。 根据设计结构，写指针和读指针被用于使数据能够异步地从第一时钟域发送到第二时钟域。
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公开(公告)号：US20080195774A1
公开(公告)日：2008-08-14
申请号：US12105449
申请日：2008-04-18
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.
摘要翻译： 公开了一种体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构，包括用于接口系统的设计结构。 该系统包括缓冲器，其从第一时钟域中的源接收数据，并将要由目的地读取的数据存储在第二时钟域中，其中缓冲器在第一时钟域和第二时钟域两者中起作用; 一个写入指针，指向由源写入的数据; 以及指向目的地读取的数据的读指针。 根据设计结构，写指针和读指针被用于使数据能够异步地从第一时钟域发送到第二时钟域。
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