公开(公告)号：US20210050200A1

公开(公告)日：2021-02-18

申请号：US16889700

申请日：2020-06-01

Applicant: Brigham Young University

Inventor： Yixin Song ,  Shiuh-hua Wood Chiang ,  Aaron R. Hawkins ,  Daniel E. Austin

IPC: H01J49/02 ,  G01R29/24 ,  H03F3/45 ,  H03F3/70 ,  H03G3/30

Abstract: The present invention is a system and method for providing a charge detector that utilizes small feedback capacitors in a low-noise, high-gain, system that combines a differential topology in a solid-state amplifier implemented in a complementary metal-oxide semiconductor (CMOS) process with active reset, thereby achieving high dynamic range and robust operations. A custom optoelectronic system is used to measure gain, and while operating at a sampling frequency of 10 kHz, the active reset extends the dynamic range of the charge detector.

公开(公告)号：US11443930B2

公开(公告)日：2022-09-13

申请号：US16889700

申请日：2020-06-01

Applicant: Brigham Young University

Inventor： Yixin Song ,  Shiuh-hua Wood Chiang ,  Aaron R. Hawkins ,  Daniel E. Austin

IPC: H01J49/02 ,  G01R29/24 ,  H03F3/45 ,  H03G3/30 ,  H03F3/70

Abstract: The present invention is a system and method for providing a charge detector that utilizes small feedback capacitors in a low-noise, high-gain, system that combines a differential topology in a solid-state amplifier implemented in a complementary metal-oxide semiconductor (CMOS) process with active reset, thereby achieving high dynamic range and robust operations. A custom optoelectronic system is used to measure gain, and while operating at a sampling frequency of 10 kHz, the active reset extends the dynamic range of the charge detector.

公开(公告)号：US11101814B2

公开(公告)日：2021-08-24

申请号：US17030201

申请日：2020-09-23

Applicant: BRIGHAM YOUNG UNIVERSITY

Inventor： Shiuh-hua Wood Chiang ,  Yixin Song ,  Eric Swindlehurst ,  Jensen Hunter ,  Yen-Cheng Kuan

IPC: H03M1/66 ,  H03M1/46 ,  H03M1/00 ,  H03M1/06

Abstract: The present invention is a system and method for providing a modified Digital-to-Analog converter (DAC) for use in a time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC), the DAC including grouping of capacitance electrodes by Bit in a DAC, thereby reducing parasitic capacitances, and substantially improving power efficiency and speed to operate at GHz frequencies.

公开(公告)号：US20210091781A1

公开(公告)日：2021-03-25

申请号：US17030201

申请日：2020-09-23

Applicant: BRIGHAM YOUNG UNIVERSITY

Inventor： Shiuh-hua Wood Chiang ,  Yixin Song ,  Eric Swindlehurst ,  Jensen Hunter ,  Yen-Cheng Kuan

IPC: H03M1/46 ,  H03M1/06 ,  H03M1/00

Abstract: The present invention is a system and method for providing a modified Digital-to-Analog converter (DAC) for use in a time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC), the DAC including grouping of capacitance electrodes by Bit in a DAC, thereby reducing parasitic capacitances, and substantially improving power efficiency and speed to operate at GHz frequencies.