公开(公告)号：US09093134B2

公开(公告)日：2015-07-28

申请号：US13725109

申请日：2012-12-21

Applicant: Broadcom Corporation

Inventor： Binfan Liu ,  Junyi Xu

IPC: G11C29/00 ,  G11C7/10 ,  H03M13/27 ,  H03M13/29

CPC classification number: G11C7/1072 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/2936

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract translation: 提供了使用外部DDR SDRAM执行高速多通道前向纠错的系统和方法。 根据一个示例性方面，交织器/解交织器通过隐藏有效和预充电周期来对通过突发定向的DDR SDRAM执行读和写访问，以实现高数据速率操作。 交织器/解交织器将DDR SDRAM中的数据作为读取块和写入块访问。 每个块包括两个数据序列。 每个数据序列还包括要交织/解交织的预定数量的数据字。 当正在处理前面的数据序列时，会发出一个数据序列的PRECHARGE和ACTIVE命令。 一个读/写数据序列中的数据在DDR SDRAM的同一组内具有相同的行地址。

公开(公告)号：US20170034544A1

公开(公告)日：2017-02-02

申请号：US14812531

申请日：2015-07-29

Applicant: Broadcom Corporation

Inventor： Weimin ZHANG ,  Binfan Liu

IPC: H04N21/2365 ,  H04N21/2385 ,  H04N21/2383 ,  H04N21/222 ,  H04N21/2343

CPC classification number: H04N21/2365 ,  H04N21/2221 ,  H04N21/234309 ,  H04N21/2383 ,  H04N21/2385

Abstract: The present disclosure is directed to a system and method for creating overlapping bonded groups of downstream channels that can provide increased channel capacity to improve packing densities, while at the same time limiting complexity and cost increases of new receivers and allowing the continued operation of legacy receivers.

Abstract translation: 本公开涉及一种用于创建下游信道的重叠绑定组的系统和方法，其可以提供增加的信道容量以提高包装密度，同时限制新接收机的复杂性和成本增加并允许传统接收机的继续操作 。

公开(公告)号：US08873647B2

公开(公告)日：2014-10-28

申请号：US13767625

申请日：2013-02-14

Applicant: Broadcom Corporation

Inventor： Binfan Liu ,  Junyi Xu ,  Weimin Zhang

IPC: H04B3/00 ,  H04L7/00 ,  H03L7/06 ,  H04J3/06 ,  H04L27/36

CPC classification number: H04L7/0037 ,  H03L7/06 ,  H04J3/0638 ,  H04J3/0658 ,  H04L27/36

Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.

Abstract translation: 在EQAM设备中支持多个参考时钟的高效同步技术。 考虑在EQAM设备中接收来自具有对应的不同定时参考（即，不同的源参考时钟）的相应多个不同源的数据的多个不同调制器。 为了适应这一点，调制器都使用公共系统时钟进行操作，并且每个调制器都配备有相位同步器。 相位同步器将调制的符号相位同步到相应的参考时钟。