公开(公告)号：US20150108558A1

公开(公告)日：2015-04-23

申请号：US14578924

申请日：2014-12-22

Applicant: Broadcom Corporation

Inventor： Wei XIA ,  Xiangdong Chen

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/0811 ,  H01L27/092 ,  H01L28/60 ,  H01L28/65 ,  H01L29/4232 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps.

Abstract translation: 根据一个实施例，半导体管芯中的可扩展集成MIM电容器包括衬底上的高k电介质段和高k电介质段上的金属段，其中金属段形成集成MIM电容器的电容器端子。 电容器还包括横向分离连续的电容器端子的填料，其中填料可以用作集成MIM电容器的电容器电介质。 在一个实施例中，金属段包括栅极金属。 在另一个实施例中，集成MIM电容器基本上与一个或多个晶体管同时形成，而不需要额外的制造工艺步骤。

公开(公告)号：US20130288439A1

公开(公告)日：2013-10-31

申请号：US13924115

申请日：2013-06-21

Applicant: Broadcom Corporation

Inventor： Wei XIA ,  Xiangdong Chen

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0629 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2924/12035 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

Abstract translation: 垂直堆叠的平面结齐纳二极管与外延生长的FET升高的S / D端子同时形成。 齐纳二极管的结构和工艺与Gate-Last高k FET结构和工艺兼容。 二极管和晶体管结构的横向分离由改进的STI屏蔽提供。 不需要额外的光刻步骤。 在一些实施例中，最上面的二极管端子的非结面用镍硅化，以另外作为铜扩散阻挡层。