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公开(公告)号:US20190244966A1
公开(公告)日:2019-08-08
申请号:US16385674
申请日:2019-04-16
申请人: ROHM CO., LTD.
发明人: Yuichi NAKAO
IPC分类号: H01L27/11507 , H01L49/02 , H01L27/11502
CPC分类号: H01L27/11507 , H01L27/11502 , H01L28/55 , H01L28/57 , H01L28/60 , H01L28/65 , H01L28/75
摘要: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.
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公开(公告)号:US20190172903A1
公开(公告)日:2019-06-06
申请号:US16272736
申请日:2019-02-11
申请人: Invensas Corporation
发明人: Liang Wang , Hong Shen , Rajesh Katkar
IPC分类号: H01L49/02 , H01L23/00 , H01L21/56 , H01L23/522 , H01L25/00 , H01L25/16 , H01L25/11 , H01L25/10 , H01L23/498
CPC分类号: H01L28/60 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/5223 , H01L24/05 , H01L24/32 , H01L24/83 , H01L25/105 , H01L25/11 , H01L25/115 , H01L25/165 , H01L25/50 , H01L28/40 , H01L28/65 , H01L2224/05009 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/1205 , H01L2924/15311 , H01L2924/16153 , H01L2924/00
摘要: Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.
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3.
公开(公告)号:US20190103151A1
公开(公告)日:2019-04-04
申请号:US16194820
申请日:2018-11-19
IPC分类号: G11C11/22 , H01L27/11507 , H01L49/02 , G11C13/04 , H01L27/11502 , G11C14/00 , G11C11/56
CPC分类号: G11C11/225 , G11C11/22 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/2297 , G11C11/5657 , G11C13/047 , G11C14/00 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L28/65 , H01L28/75
摘要: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.
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公开(公告)号:US20180247997A1
公开(公告)日:2018-08-30
申请号:US15901498
申请日:2018-02-21
申请人: BlackBerry Limited
CPC分类号: H01L28/40 , H01L21/02183 , H01L21/02186 , H01L21/02197 , H01L21/02266 , H01L21/0228 , H01L21/02282 , H01L21/02304 , H01L21/02356 , H01L28/56 , H01L28/65 , H01L28/75
摘要: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.
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公开(公告)号:US09991270B2
公开(公告)日:2018-06-05
申请号:US15623710
申请日:2017-06-15
发明人: Wensheng Wang
IPC分类号: H01L27/11507 , H01L49/02 , H01L21/324 , H01L21/768
CPC分类号: H01L27/11507 , H01L21/324 , H01L21/7687 , H01L21/76897 , H01L28/57 , H01L28/65 , H01L28/75
摘要: A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.
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公开(公告)号:US09831255B2
公开(公告)日:2017-11-28
申请号:US15221756
申请日:2016-07-28
申请人: ROHM CO., LTD.
发明人: Yuichi Nakao
IPC分类号: H01L27/115 , H01L27/11507 , H01L49/02 , H01L27/11502
CPC分类号: H01L27/11507 , H01L27/11502 , H01L28/55 , H01L28/57 , H01L28/60 , H01L28/65 , H01L28/75
摘要: A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.
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7.
公开(公告)号:US09679960B2
公开(公告)日:2017-06-13
申请号:US15177640
申请日:2016-06-09
发明人: Kuo-Chi Tu
IPC分类号: H01L21/8242 , H01L49/02 , H01L21/3213
摘要: Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.
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公开(公告)号:US09673269B2
公开(公告)日:2017-06-06
申请号:US13225451
申请日:2011-09-04
申请人: Emmanuel Defay , Gwenaël Le Rhun , Aurélien Suhm
发明人: Emmanuel Defay , Gwenaël Le Rhun , Aurélien Suhm
CPC分类号: H01L28/55 , H01L21/02197 , H01L21/02282 , H01L28/40 , H01L28/65
摘要: An integrated capacitor comprises a layer of dielectric material known as functional dielectric material based on crystallized material of perovskite type, between at least one first electrode known as a bottom electrode at the surface of a substrate and at least one second electrode known as a top electrode, said electrodes being electrically insulated by a layer of electrically insulating material in order to allow at least one contact on the top electrode. The electrically insulating material is made of an amorphous dielectric material of perovskite type having a dielectric constant lower than that of the crystallized material of perovskite type. The contact is formed from an etched contacting layer in contact with the electrically insulating dielectric layer level with its surface parallel to the plane of the layers. A process for manufacturing such an integrated capacitor is also provided.
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公开(公告)号:US20170117282A1
公开(公告)日:2017-04-27
申请号:US15334278
申请日:2016-10-25
申请人: Intermolecular, Inc.
IPC分类号: H01L27/108 , H01L49/02
CPC分类号: H01L27/10852 , H01L27/10814 , H01L27/11582 , H01L28/00 , H01L28/56 , H01L28/65
摘要: Embodiments provided herein describe capacitor stacks and methods for forming capacitor stacks. A first electrode is formed above a substrate. A dielectric layer is formed above the first electrode. The dielectric layer includes zirconium. A second electrode is formed above the dielectric layer. At least one of the first electrode and the second electrode includes iridium.
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公开(公告)号:US20170084607A1
公开(公告)日:2017-03-23
申请号:US15365237
申请日:2016-11-30
发明人: Hartmud Terletzki
IPC分类号: H01L27/06 , H01L21/8234 , H01L29/94 , H01L29/06 , H01L29/66 , H01L21/762 , H01L27/02
CPC分类号: H01L27/0629 , H01L21/76224 , H01L21/823481 , H01L27/0207 , H01L28/40 , H01L28/65 , H01L29/0653 , H01L29/66181 , H01L29/945
摘要: A method of forming a semiconductor device includes providing a semiconductor substrate including a source/drain region, an active transistor region, and a substrate contact region coupled to a body region. A shallow trench isolation (STI) area is formed in a major surface of the semiconductor substrate in between the active transistor region and the substrate contact region. The method further includes at least partially burying at least one capacitor in the STI area.
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