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1.发明授权
公开(公告)号：US5760784A
公开(公告)日：1998-06-02
申请号：US589212
申请日：1996-01-22
CPC分类号： G06T9/00
摘要： Video data is decompressed in a coder/decoder (CODEC) and then scaled in a scaler device before being provided to a frame buffer within a display adapter of a data processing system. Since the scaling of the video data often results in a significant increase in the required bandwidth, a buffer implemented within the scaling device may reach a threshold level whereby it is not desired that any more scaled data be received before being transmitted to the frame buffer. When such a threshold level is reached, a stall signal is sent to the interface between the scaler device and the CODEC device providing the pixel data, which results in the stopping of the transmission of pixel data from the CODEC to the scaler device. Assertion of the stall signal results in the suspension of the transmission of the horizontal and vertical synchronization signals and the pixel clock signal from the scaler device to the CODEC device.
摘要翻译： 视频数据在编码器/解码器（CODEC）中解压缩，然后在缩放器装置中被缩放，然后提供给数据处理系统的显示适配器内的帧缓冲器。 由于视频数据的缩放通常导致所需带宽的显着增加，所以在缩放设备内实现的缓冲器可能达到阈值水平，因此不希望在发送到帧缓冲器之前接收任何更多的缩放数据。 当达到这样的阈值电平时，向缩放器装置和提供像素数据的CODEC装置之间的接口发送失速信号，这导致停止从CODEC到缩放装置的像素数据传输。 失速信号的断言导致水平和垂直同步信号和像素时钟信号从缩放器装置传输到CODEC装置的暂停。
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公开(公告)号：US06876664B1
公开(公告)日：2005-04-05
申请号：US09541773
申请日：2000-04-03
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9063
摘要： An improved asynchronous data buffer is disclosed. The data buffer comprises an entry section and a signaling circuit coupled to the entry section, the signaling circuit for signaling the data buffer to transfer a portion of a data cell from the entry section prior to the data cell being completely received by the entry section. Through the use of the data buffer in accordance with the present invention, data transfer systems are improved in two ways. Firsts by enabling data to be transferred before it is completely stored into the buffer, the latency that is typically required for data cell transfer is reduced. Second, the buffer storage space that is typically required to store a complete data cell is also reduced. This twofold improvement produces increased data transfer rates while decreasing the amount of required buffer storage space.
摘要翻译： 公开了一种改进的异步数据缓冲器。 数据缓冲器包括一个入口部分和一个耦合到入口部分的信令电路，该信令电路用于在数据单元被入口部分完全接收之前，用于发信号通知数据缓冲器以从入口部分传输数据单元的一部分。 通过使用根据本发明的数据缓冲器，数据传输系统以两种方式被改进。 首先，在将数据完全存储到缓冲器之前，使数据能够传输，减少数据单元传输通常需要的延迟。 第二，通常需要存储完整数据单元的缓冲存储空间也减少了。 这种双重改进在减少所需缓冲存储空间的量的同时增加了数据传输速率。
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公开(公告)号：US06519757B1
公开(公告)日：2003-02-11
申请号：US09546982
申请日：2000-04-11
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Descriptive statements representative of a communication level coupling the functional logic of an integrated circuit to the external environment is translated into complex functional specification language for input to hardware design programs. Plain language within the functional specifications is converted to proper design language to implement hardware described by the functional specification.
摘要翻译： 表示将集成电路的功能逻辑耦合到外部环境的通信级别的描述性语句被转换成用于输入到硬件设计程序的复杂功能规范语言。 功能规范中的普通语言被转换为适当的设计语言，以实现由功能规范描述的硬件。
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4.发明授权Method and system for providing hierarchical self-checking in ASIC simulation 失效在ASIC仿真中提供分层自检的方法和系统公开(公告)号：US07072816B1
公开(公告)日：2006-07-04
申请号：US09409940
申请日：1999-09-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.
摘要翻译： 公开了一种用于在集成电路开发期间提供集成电路的仿真的方法和系统。 集成电路具有包括接口的岛。 该方法和系统包括一个窥探者，一个检查器和一个生成器。 监听器与接口耦合，用于在仿真期间获得由岛提供的输出。 检查器与接口耦合，用于检查输出以确定输出是否是期望的输出。 发生器与接口耦合，用于在仿真期间向接口提供输入。 发电机与引导发电机的测试箱相连。
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