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1.发明授权
公开(公告)号：US5760784A
公开(公告)日：1998-06-02
申请号：US589212
申请日：1996-01-22
CPC分类号： G06T9/00
摘要： Video data is decompressed in a coder/decoder (CODEC) and then scaled in a scaler device before being provided to a frame buffer within a display adapter of a data processing system. Since the scaling of the video data often results in a significant increase in the required bandwidth, a buffer implemented within the scaling device may reach a threshold level whereby it is not desired that any more scaled data be received before being transmitted to the frame buffer. When such a threshold level is reached, a stall signal is sent to the interface between the scaler device and the CODEC device providing the pixel data, which results in the stopping of the transmission of pixel data from the CODEC to the scaler device. Assertion of the stall signal results in the suspension of the transmission of the horizontal and vertical synchronization signals and the pixel clock signal from the scaler device to the CODEC device.
摘要翻译： 视频数据在编码器/解码器（CODEC）中解压缩，然后在缩放器装置中被缩放，然后提供给数据处理系统的显示适配器内的帧缓冲器。 由于视频数据的缩放通常导致所需带宽的显着增加，所以在缩放设备内实现的缓冲器可能达到阈值水平，因此不希望在发送到帧缓冲器之前接收任何更多的缩放数据。 当达到这样的阈值电平时，向缩放器装置和提供像素数据的CODEC装置之间的接口发送失速信号，这导致停止从CODEC到缩放装置的像素数据传输。 失速信号的断言导致水平和垂直同步信号和像素时钟信号从缩放器装置传输到CODEC装置的暂停。
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2.发明授权Method and apparatus for synchronizing video and graphics data in a multimedia display system including a shared frame buffer 失效一种用于在包括共享帧缓冲器的多媒体显示系统中同步视频和图形数据的方法和装置
公开(公告)号：US5977989A
公开(公告)日：1999-11-02
申请号：US922000
申请日：1997-09-02
CPC分类号： G09G5/12 , G09G2340/125 , H04N5/073 , H04N9/641 , Y10S715/972
摘要： A multimedia display system includes a central processing unit, a storage device associated with the central processing unit, a standard interface bus to which the central processing unit and the storage device are connected, a graphics processor connected to the bus for generating graphics data in response to commands from the central processor, a digitizer for converting an analog video signal to digital form and for producing synchronization signals, a video processor for processing the digitized video data to produce pixel representations of the digitized video signal, a shared frame buffer for storing the graphics data generated by the graphics processor and the pixel representations of the video signal, a device for converting the stored digital data to a data stream appropriate for driving a video monitor, and a video monitor for displaying the graphics data and the video information, wherein the video processor generates a programmable variable phase vertical synchronization signal for synchronizing video data and graphics data through a shared frame buffer with the capacity to handle relocatable windows.
摘要翻译： 多媒体显示系统包括中央处理单元，与中央处理单元相关联的存储设备，连接中央处理单元和存储设备的标准接口总线，连接到总线的图形处理器，用于响应于生成图形数据 来自中央处理器的命令，用于将模拟视频信号转换为数字形式并用于产生同步信号的数字转换器，用于处理数字化视频数据以产生数字化视频信号的像素表示的视频处理器，用于存储数字视频信号的共享帧缓冲器 由图形处理器生成的图形数据和视频信号的像素表示，用于将存储的数字数据转换成适用于驱动视频监视器的数据流的装置，以及用于显示图形数据和视频信息的视频监视器，其中 视频处理器产生可编程可变相位垂直同步信号 用于通过具有处理可重定位窗口的能力的共享帧缓冲器来同步视频数据和图形数据。
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公开(公告)号：US06347294B1
公开(公告)日：2002-02-12
申请号：US09158267
申请日：1998-09-22
IPC分类号： G06F1300
CPC分类号： G06F13/4068
摘要： A system and method in accordance with the present invention provides for an embedded CPU system which is upgradeable through the use of an external CPU which can be utilized therewith. In a first aspect, the embedded CPU system includes a CPU and a plurality of devices which are accessible by the CPU, via a device control register bus. The embedded CPU system includes logic coupled to the device control register bus for allowing access to the devices within the embedded CPU system by an external CPU. In a preferred embodiment the present invention provides a highly integrated set top box controller with a processor performance that services the low-end with the added advantage of additional performance with the EMCPU operating as an I/O assist processor to the EXCPU. When the EXCPU operates as the primary processor these two processors serve as a high end set top box controller. A system and method in accordance with the present invention can also preserve much of the software programming model when migrating from a low end processor set top box controller to a higher end solution. A system and method in accordance with the present invention also offers a choice of preserving much of the existing software investment by allowing different processor architectures to function as the EXCPU.
摘要翻译： 根据本发明的系统和方法提供了一种嵌入式CPU系统，其可通过使用可与其一起使用的外部CPU来升级。 在第一方面，嵌入式CPU系统包括CPU和可由CPU通过设备控制寄存器总线访问的多个设备。 嵌入式CPU系统包括耦合到设备控制寄存器总线的逻辑，用于允许外部CPU访问嵌入式CPU系统内的设备。 在优选实施例中，本发明提供了一种具有处理器性能的高度集成的机顶盒控制器，该处理器性能使得EMCPU作为对EXCPU的I / O辅助处理器进行操作，具有附加性能的额外优点，从而为低端服务。 当EXCPU作为主处理器运行时，这两个处理器用作高端机顶盒控制器。 根据本发明的系统和方法还可以在从低端处理器机顶盒控制器迁移到较高端解决方案时保留大部分软件编程模型。 根据本发明的系统和方法还提供了通过允许不同处理器架构作为EXCPU起作用来保留大量现有软件投资的选择。
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公开(公告)号：US5764964A
公开(公告)日：1998-06-09
申请号：US322673
申请日：1994-10-13
CPC分类号： G09G5/393 , G09G5/14 , G09G2340/125
摘要： The display buffer of a multimedia workstation is partitioned into a display section and a non-display section. The information to be displayed on the display screen is arranged in the display section of the display buffer. An image or shadow of the display section is written in the non-display section (called a lock buffer) of the display buffer. Prior to updating the display section, a controller reads the protection data from the lock buffer and generates control signals which inhibit the writing of data into protected areas of the display section.
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5.发明授权Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration 失效交叉条交换机中的低延迟数据路径提供动态优先的总线仲裁公开(公告)号：US06275890B1
公开(公告)日：2001-08-14
申请号：US09136595
申请日：1998-08-19
申请人： William Robert Lee , David Wallach
发明人： William Robert Lee , David Wallach
IPC分类号： G06F1300
CPC分类号： G06F13/36
摘要： The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a manner of switching for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a manner of configuration for prioritizing access requests by the plurality of master buses to the plurality of slave buses via the switching means. The cross-bar switch of the present invention has the capability of prioritizing requests between multiple parallel high speed buses. In a preferred embodiment, this arbitration is accomplished through Configuration Registers on the cross-bar switch. The Configuration Registers are programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmed and changed by a processor in a larger system. The cross-bar switch of the present invention minimizes the latency between data transfers. This improves the bandwidth and throughput on the on-chip bus.
摘要翻译： 本发明提供一种交叉开关，其包括多个主总线端口，主总线端口适于接收多个主总线; 多个从属总线端口，所述从属总线端口适于接收多个从属总线; 用于选择性地将多个主总线端口耦合到多个从属总线端口的切换方式; 以及用于经由切换装置将多个主总线的访问请求优先于多个从总线的配置方式。 本发明的交叉开关具有在多个并行高速总线之间优先化请求的能力。 在优选实施例中，该仲裁通过交叉开关上的配置寄存器来实现。 配置寄存器可通过器件控制寄存器总线进行编程，允许跨系统开关由较大系统中的处理器进行动态编程和更改。 本发明的交叉开关将数据传输之间的延迟最小化。 这样可以提高片上总线的带宽和吞吐量。
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6.发明授权Dynamically configurable variable frequency and duty cycle clock and signal generation 失效动态配置的可变频率和占空比时钟和信号产生
公开(公告)号：US6040725A
公开(公告)日：2000-03-21
申请号：US89757
申请日：1998-06-02
CPC分类号： H03K5/1565 , G06F1/025 , H03K5/00006 , H03K5/135
摘要： A variable clock generator includes a clock multiplier that generates from a reference clock at least two clock signals which are out of phase with each other and a clock divider which receives a plurality of divider patterns and which receives at least two clock signals from the clock multiplier. The clock divider generates an output clock based on the divider patterns and the clock signals. In a particular embodiment, the clock divider includes a plurality of loadable linear feedback shift registers each having an output. An EXCLUSIVE OR gate that is responsive to the outputs of the linear feedback shift registers then EXCLUSIVE ORs the outputs of the linear feedback shift registers to produce the output clock. Preferably, the size of the linear feedback shift registers corresponds to the size of the divider patterns.
摘要翻译： 可变时钟发生器包括时钟乘法器，其从参考时钟产生彼此不同相的至少两个时钟信号，以及时钟分频器，其接收多个分频器模式并从时钟乘法器接收至少两个时钟信号 。 时钟分频器基于分频器模式和时钟信号产生输出时钟。 在特定实施例中，时钟分配器包括多个可负载的线性反馈移位寄存器，每个具有输出。 响应于线性反馈移位寄存器的输出的EXCLUSIVE或门，EXCLUSIVE或使线性反馈移位寄存器的输出产生输出时钟。 优选地，线性反馈移位寄存器的大小对应于分频器模式的大小。
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公开(公告)号：US06192486B1
公开(公告)日：2001-02-20
申请号：US09133395
申请日：1998-08-13
IPC分类号： G06F1100
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： The present invention provides a method and system for bypassing defective sections with a memory array of a computer chip. The circuit in accordance with the present invention includes a register for controlling the effective size of the memory array based upon the detection of at least one defective section in the memory array, and a multiplexer for receiving an index address for the memory array and for the mapping of the index address based upon the register means. The circuit in accordance with the present invention does not use fuses to conduct repairs and thus does not require additional area on the chip for such fuses. As such, it eliminates the complications in the manufacturing process related to fuses and redundant cells. The circuit in accordance with the present invention dynamically manipulates the address of the array to bypass the defective regions of the array. Although the present invention results in a reduction in the overall size of the array, and thus may result in performance degradation, it allows for the continued operation of the chip. For an embedded memory, the chip need not be discarded. Importantly, unlike the conventional method, the circuit in accordance with the present invention has the ability to handle defects which are introduced during usage, and defect detection and bypass are initiated each time the computer is initialized. Thus, the circuit in accordance with the present invention has utility subsequent to manufacturing testing. A chip with embedded memory which has the steering circuit of the present invention is thus more reliable than memory chips repaired with conventional methods.
摘要翻译： 本发明提供一种利用计算机芯片的存储器阵列绕过缺陷部分的方法和系统。 根据本发明的电路包括：寄存器，用于基于对存储器阵列中的至少一个缺陷部分的检测来控制存储器阵列的有效大小，以及多路复用器，用于接收存储器阵列的索引地址， 基于寄存器装置映射索引地址。 根据本发明的电路不使用保险丝进行维修，因此不需要芯片上用于这种保险丝的附加区域。 因此，它消除了与保险丝和冗余电池相关的制造过程中的复杂性。 根据本发明的电路动态地操纵阵列的地址以绕过阵列的缺陷区域。 尽管本发明导致阵列的总体尺寸的减小，并且因此可能导致性能下降，但是它允许芯片的继续操作。 对于嵌入式存储器，芯片不需要丢弃。 重要的是，与传统方法不同，根据本发明的电路具有处理使用期间引入的缺陷的能力，并且每当计算机初始化时启动缺陷检测和旁路。 因此，根据本发明的电路在制造测试之后具有实用性。 具有本发明的转向电路的具有嵌入式存储器的芯片因此比用常规方法修复的存储器芯片更可靠。
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公开(公告)号：US5694585A
公开(公告)日：1997-12-02
申请号：US337697
申请日：1994-11-10
IPC分类号： G06F13/16
CPC分类号： G06F13/1689
摘要： A programmable memory controller includes a plurality of multi-bit registers, with each multi-bit register coupled to a cycle generator. Each cycle generator is formed from a multi-bit shift register and control signals which drive each multi-bit shift register so that data in an associated multi-bit register is shifted through the shift register to form desired memory control pulses.
摘要翻译： 可编程存储器控制器包括多个多位寄存器，每个多位寄存器耦合到周期发生器。 每个周期发生器由多位移位寄存器和驱动每个多位移位寄存器的控制信号形成，使得相关联的多位寄存器中的数据通过移位寄存器移位以形成期望的存储器控制脉冲。
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9.发明授权公开(公告)号：US06970816B1
公开(公告)日：2005-11-29
申请号：US09638268
申请日：2000-08-14
申请人： Paul David Bryan , Richard Gerard Hofmann , Peter Dean LaFauci , William Robert Lee , Rhonda Gurganious Mitchell , Timothy Patrick Oke
发明人： Paul David Bryan , Richard Gerard Hofmann , Peter Dean LaFauci , William Robert Lee , Rhonda Gurganious Mitchell , Timothy Patrick Oke
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and system for efficiently generating parameterized bus transactions for verification of a design-under-test (DUT) comprises providing a configuration file for the DUT to a generator program. The configuration file defines possible parameter combinations for bus transactions executable by the DUT, and the generator program systematically enumerates all the possible combinations to produce a test case for verifying the DUT. Rules specified within the configuration file can include or exclude selected parameter combinations to tailor the test case to a specific DUT-to-bus interface.
摘要翻译： 用于有效地产生用于验证被测设计（DUT）的参数化总线事务的方法和系统包括向发生器程序提供DUT的配置文件。 配置文件定义可由DUT执行的总线事务的可能参数组合，并且生成器程序系统地枚举所有可能的组合以产生用于验证DUT的测试用例。 在配置文件中指定的规则可以包括或排除选定的参数组合，以将测试用例定制到特定的DUT到总线接口。
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公开(公告)号：US06323755B1
公开(公告)日：2001-11-27
申请号：US09136023
申请日：1998-08-19
申请人： William Robert Lee , David Wallach
发明人： William Robert Lee , David Wallach
IPC分类号： H04M514
CPC分类号： G06F13/4022
摘要： A cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a switching mechanism for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a configuration mechanism for locking at least one of the plurality of slave buses in response to a transfer request initiated by a master device attached to one of the plurality of master buses. The cross-bar switch has the capability of selectively locking slave buses during a bus lock transfer. In the preferred embodiment, the configuration mechanism is a Bus Lock Bit on Configuration Registers on the cross-bar switch. The Bus Lock Bit is programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmable and changed by a processor in a larger system. The cross-bar switch minimizes the cycle latency between data transfers. This improves the bandwidth and throughput on the on-chip bus.
摘要翻译： 一种横杆开关，其包括多个主总线端口，所述主总线端口适于接收多个主总线; 多个从属总线端口，所述从属总线端口适于接收多个从属总线; 用于选择性地将多个主总线端口耦合到多个从属总线端口的切换机构; 以及用于响应于由附接到所述多个主总线之一的主设备发起的传送请求而锁定所述多个从属总线中的至少一个的配置机构。 交叉开关具有在总线锁传输期间选择性地锁定从站总线的能力。 在优选实施例中，配置机制是在横杆开关上的配置寄存器上的总线锁定位。 总线锁定位可通过器件控制寄存器总线进行编程，允许交叉开关由较大系统中的处理器动态编程和更改。 交叉开关最小化数据传输之间的周期延迟。 这样可以提高片上总线的带宽和吞吐量。
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