公开(公告)号：US20080162799A1

公开(公告)日：2008-07-03

申请号：US11648483

申请日：2006-12-28

申请人： Bryan Spry ,  Nagi Aboulenein ,  Steve Kulick

发明人： Bryan Spry ,  Nagi Aboulenein ,  Steve Kulick

IPC分类号： G06F13/14

CPC分类号： G06F13/1642

摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes a scheduler to schedule memory transactions to the DIMM and a write address queue to accumulate the write requests while the memory controller is operating in a first mode and to release the write requests to the scheduler whenever the memory controller is operating in a second mode.

摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括调度器，用于在存储器控制器以第一模式操作时调度到DIMM的存储器事务和写入地址队列以累积写请求，并且每当存储器控制器在 第二模式。

公开(公告)号：US20070156971A1

公开(公告)日：2007-07-05

申请号：US11323368

申请日：2005-12-29

申请人： Krishnakanth Sistla ,  Bryan Spry

发明人： Krishnakanth Sistla ,  Bryan Spry

IPC分类号： G06F13/28

CPC分类号： G06F12/084 ,  G06F12/0822 ,  G06F12/0831 ,  G06F2212/306

摘要： A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always able to complete a monitor transaction without requiring self snooping through the system interconnect.

摘要翻译： 当处理器采用包含共享的最后一级高速缓存时，实现监视器原语的方法和装置。 通过采用包容性最后一级缓存，处理器几乎总是能够完成监视器事务，而不需要通过系统互连自窥。

公开(公告)号：US20070005865A1

公开(公告)日：2007-01-04

申请号：US11171974

申请日：2005-06-29

申请人： Bryan Spry ,  Jeffrey Gilbert

发明人： Bryan Spry ,  Jeffrey Gilbert

IPC分类号： G06F13/36

CPC分类号： G06F13/1663 ,  G06F12/0831 ,  G06F2212/306

摘要： An arrangement is provided for efficiently enforcing global ordering in a computing system using an inter-queue ordering mechanism (IQOM). The IQOM may be located in a bridge (e.g., a caching bridge) coupling two interconnects: an internal interconnect to connect different processing units (e.g., processing cores inside a processor or a single core processor) and a system interconnect to connect different processors and/or different internal interconnects. The bridge handles transactions from two directions: inbound—from the system interconnect to an internal interconnect, and outbound—from an internal interconnect to the system interconnect. The IQOM may be used to enforce strict ordering among inbound transactions and among outbound transactions separately and thus allow certain inbound transactions that occur on the system interconnect after an outbound transaction to be completed before the outbound transaction.

摘要翻译： 提供了一种用于使用队列间排序机制（IQOM）在计算系统中有效地实施全局排序的布置。 IQOM可以位于耦合两个互连的桥（例如，缓存桥）中：内部互连以连接不同的处理单元（例如，处理器或单核处理器内的处理核）和连接不同处理器的系统互连 /或不同的内部互连。 桥接器处理来自两个方向的事务：入站 - 从系统互连到内部互连，以及出站 - 从内部互连到系统互连。 IQOM可用于在入站事务和出站事务之间分别执行严格的排序，从而允许在出站事务完成出站事务之后在系统互连上发生的某些入站事务。

公开(公告)号：US20060218334A1

公开(公告)日：2006-09-28

申请号：US11087914

申请日：2005-03-22

申请人： Bryan Spry ,  Harris Joyce ,  Balaji Ramamoorthy ,  Jeffrey Gilbert

发明人： Bryan Spry ,  Harris Joyce ,  Balaji Ramamoorthy ,  Jeffrey Gilbert

IPC分类号： G06F13/36

CPC分类号： G06F13/1615

摘要： A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. When the responding agent knows that the requested data will shortly arrive in its buffers, it may first send an identification signal to the requesting agent, indicating to the requesting agent that it should prepare to receive the data shortly. After one or more bus clock cycles, the responding agent may then subsequently send the corresponding data message to the requesting agent.

摘要翻译： 描述了用于在总线连接系统中用信号通知延迟响应到数据请求的系统和方法。 在一个实施例中，总线上的响应代理在短时间内不能提供所请求的数据时发出延迟响应消息。 当响应代理知道请求的数据将很快到达其缓冲器时，它可以首先向请求代理发送标识信号，向请求代理指示应该准备好在短时间内接收数据。 在一个或多个总线时钟周期之后，响应代理随后可以将相应的数据消息发送到请求代理。