公开(公告)号：US20020083278A1

公开(公告)日：2002-06-27

申请号：US09746240

申请日：2000-12-22

申请人： Bull HN Information Systems Inc.

发明人： Bruce A. Noyes

IPC分类号： G06F012/00

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/30174

摘要： Atomic multiple word writes are provided when emulating a target system that supports atomic multiple word writes on a host system that does not. For each except the last word to be written, a gate flag is read, tested, and locked when it is found unlocked. The words are then written to memory in reverse order, unlocking the gate flags as they are written. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.

摘要翻译： 当在不支持原子多字写入的主机系统上模拟目标系统时，提供原子多字写入。 对于除写入的最后一个字之外的每个字，当锁定被解锁时，门标志被读取，测试和锁定。 然后将这些字以相反的顺序写入存储器，在写入时对门标志进行解锁。 在具有比目标系统更长的字大小的主机系统中，门标志可以存储在主机系统字中的另外未使用的位中，其中包含要写入的目标系统字。

公开(公告)号：US20040111585A1

公开(公告)日：2004-06-10

申请号：US10309459

申请日：2002-12-04

申请人： Bull HN Information Systems Inc.

发明人： Bruce A. Noyes ,  Russell W. Guenthner

IPC分类号： G06F012/00

CPC分类号： G06F12/1027

摘要： A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter. If there is a full match, a switch issues the real page address read from the associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the associative memory is updated accordingly.

摘要翻译： 计算机系统包括中央处理单元，存储数据页和页表的可寻址主存储器和关联存储器。 关联存储器根据当CPU处理器发出的低阶虚拟地址组件访问主存储器中的给定页面时存储多个条目。 关联存储器中的每个条目包括分别保持：1）高阶虚拟地址分量的字段; 2）真实页面地址; 和3）多位数有效性计数。 CPU中可增量的多位计数器存储当前的有效性计数。 当寻求访问数据页时，比较器接收：1）数据页的高阶虚拟地址分量; 2）从关联存储器条目读取的高阶虚拟地址组件; 3）从关联存储器条目读取的多位数有效性计数; 和4）计数器中的多位数的当前有效性计数。 如果完全匹配，则交换机会发出从关联内存条目读取的真实页面地址。 如果没有匹配，则查询页表以获得所请求页面的真实地址，并且相关联的存储器被相应地更新。

公开(公告)号：US20020082822A1

公开(公告)日：2002-06-27

申请号：US09746792

申请日：2000-12-22

申请人： Bull HN Information Systems Inc.

发明人： Bruce A. Noyes

IPC分类号： G06F009/455

CPC分类号： G06F9/45554 ,  G06F9/45558 ,  G06F2009/45583

摘要： Atomic multiple word reads are provided when emulating a target system that supports atomic multiple word reads on a host system that does not. For each except the last word to be read, a gate flag is read using an advanced speculative load, and tested, until found unlocked. Check speculation instructions are utilized after the gate flag tests to verify that the corresponding cache lines have not been invalidated through a write by another processor since the speculative loads were issued. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.

摘要翻译： 当在不支持原子多重字读取的主机系统上模拟目标系统时，提供了原子多字读取。 除了要读取的最后一个字之外，还将使用高级推测负载读取门标志，并进行测试，直到找到解锁。 在门标志测试之后，检查猜测指令是否被用于验证相应的高速缓存行是否已经由另一个处理器的写入而无效，因为发布了推测负载。 在具有比目标系统更长的字大小的主机系统中，门标志可以存储在主机系统字中的另外未使用的位中，其中包含要写入的目标系统字。