公开(公告)号：US09946624B1

公开(公告)日：2018-04-17

申请号：US14960036

申请日：2015-12-04

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Alon Kfir

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/348 ,  G06F11/3041

Abstract: A system for tracing an operation of an electronic circuit is provided. The system includes an electronic circuit, a trace buffer, and a trigger detection circuit. The trace buffer includes a plurality of segments configured to continually collect and store data signals of the electronic circuit. The data signals are collected in a current segment of the plurality of segments. The trigger detection circuit is adapted to provide a trigger signal when a trigger condition is met. Each time upon generation of the trigger signal when the trigger condition is met, the collection of the data signals is stopped in the current segment and subsequent data signals are collected in a new segment of the plurality of segments.

公开(公告)号：US10540466B1

公开(公告)日：2020-01-21

申请号：US15893418

申请日：2018-02-09

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Alon Kfir ,  Jennifer Lee

IPC: G06F17/50

Abstract: An exemplary emulation computer may allocate a portion of its emulation memory for capturing probe data during a runtime of emulating a device under test (DUT). The emulation computer may instantiate a plurality of streaming probes from dynamic netlists provided by a user. The streaming probes may capture non-transitory internal signals within the DUT and transmit the captured non-transitory internal signals to the allocated portion of the emulation memory, which in turn may store the received signals as waveform data records. During the runtime of emulating the DUT, the emulation computer may receive an upload request for the waveform data records from a workstation computer. In response to the request, the emulation computer may transmit the waveform data records to the workstation computer. The emulation computer does not have to pause or stop the runtime of emulating the DUT while transmitting the data records to the workstation computer.

公开(公告)号：US10198539B1

公开(公告)日：2019-02-05

申请号：US15448436

申请日：2017-03-02

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Tsair-Chin Lin ,  Jingbo Gao ,  Alon Kfir ,  Long Wang ,  Wei Zeng ,  Zhao Li

IPC: G06F17/50

Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.