公开(公告)号：US10198539B1

公开(公告)日：2019-02-05

申请号：US15448436

申请日：2017-03-02

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Tsair-Chin Lin ,  Jingbo Gao ,  Alon Kfir ,  Long Wang ,  Wei Zeng ,  Zhao Li

IPC: G06F17/50

Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.

公开(公告)号：US10909283B1

公开(公告)日：2021-02-02

申请号：US16198163

申请日：2018-11-21

Applicant: Cadence Design Systems, Inc.

Inventor： Long Wang ,  Tsair-Chin Lin ,  Jingbo Gao

IPC: G06F30/327 ,  G06F1/28 ,  G06F30/33 ,  G06F30/398 ,  G06F111/04 ,  G06F119/06

Abstract: A method for receiving a circuit layout including modules in a hierarchical structure. The method includes selecting a module in the hierarchical structure, identifying multiple toggling netlists in the module during multiple clock cycles, grouping the toggling netlists into clusters based on a toggle weight factor, and finding an average toggle weight factor for each cluster. The method includes generating instrument logic to determine a power consumption of the circuit layout based on a number of toggling netlists in each cluster for each clock cycle, and on the average toggle weight factor for each cluster, merging, with a compiler tool, the instrument logic with the circuit layout into an executable file for an emulator tool. The method includes evaluating the power consumption of the circuit layout with the emulator tool; and modifying the circuit layout when the power consumption of the circuit layout exceeds a pre-selected threshold.