公开(公告)号：US10198539B1

公开(公告)日：2019-02-05

申请号：US15448436

申请日：2017-03-02

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Tsair-Chin Lin ,  Jingbo Gao ,  Alon Kfir ,  Long Wang ,  Wei Zeng ,  Zhao Li

IPC: G06F17/50

Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.

公开(公告)号：US20140173539A1

公开(公告)日：2014-06-19

申请号：US13719559

申请日：2012-12-19

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： David Guoqing Zhang ,  Tsair-Chin Lin

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5045 ,  G06F2217/66

Abstract: Method and apparatus for debugging aspects of integrated circuit (IC) designs employ techniques by which defective intellectual property (IP) in those IC designs can be exercised, and defects identified, without disturbing the IP itself, but at the same time isolating the source of the defect(s) to the responsible IP provider(s). The IP provider then can debug the IP. In one aspect, the techniques give the IP provider(s) specific information about the nature of the defect, facilitating the provider's efforts to debug the IP.

Abstract translation: 用于调试集成电路（IC）设计方面的方法和装置采用这些IC设计中的有缺陷的知识产权（IP）可以被执行的技术，并且识别出缺陷，而不会干扰IP本身，而是同时隔离 缺陷（一个或多个）给负责的IP提供商。 IP提供商然后可以调试IP。 在一个方面，这些技术为IP提供商提供关于缺陷性质的具体信息，便于提供商调试IP的努力。

公开(公告)号：US08739090B1

公开(公告)日：2014-05-27

申请号：US13903672

申请日：2013-05-28

Applicant: Cadence Design Systems, Inc.

Inventor： Jingbo Gao ,  Tsair-Chin Lin

IPC: G06F17/50 ,  G06F11/26

CPC classification number: G06F17/5027

Abstract: The present patent document relates a method and apparatus for compressing probe system data in hardware functional verification systems used to verify user logic designs. Such systems can create large amounts of data every data cycle, which can include many bits that do not toggle from one cycle to the next. Compressing such data is possible by arranging the data in bytes and determining which bytes contain bits that have changed. A status byte may be generated that conveys which bytes contain changed bits. Together the status byte and only the bytes that contain changed bits are transmitted to a host workstation, saving bandwidth on the communication interface.

Abstract translation: 本专利文献涉及用于在用于验证用户逻辑设计的硬件功能验证系统中压缩探测系统数据的方法和装置。 这样的系统可以在每个数据周期创建大量的数据，其可以包括不从一个周期切换到下一个周期的许多位。 通过以字节排列数据并确定哪些字节包含已更改的位，可压缩此类数据。 可以生成状态字节，其传达哪些字节包含改变的位。 将状态字节和只有包含更改位的字节一起传输到主机工作站，从而节省通信接口上的带宽。

公开(公告)号：US10909283B1

公开(公告)日：2021-02-02

申请号：US16198163

申请日：2018-11-21

Applicant: Cadence Design Systems, Inc.

Inventor： Long Wang ,  Tsair-Chin Lin ,  Jingbo Gao

IPC: G06F30/327 ,  G06F1/28 ,  G06F30/33 ,  G06F30/398 ,  G06F111/04 ,  G06F119/06

Abstract: A method for receiving a circuit layout including modules in a hierarchical structure. The method includes selecting a module in the hierarchical structure, identifying multiple toggling netlists in the module during multiple clock cycles, grouping the toggling netlists into clusters based on a toggle weight factor, and finding an average toggle weight factor for each cluster. The method includes generating instrument logic to determine a power consumption of the circuit layout based on a number of toggling netlists in each cluster for each clock cycle, and on the average toggle weight factor for each cluster, merging, with a compiler tool, the instrument logic with the circuit layout into an executable file for an emulator tool. The method includes evaluating the power consumption of the circuit layout with the emulator tool; and modifying the circuit layout when the power consumption of the circuit layout exceeds a pre-selected threshold.

公开(公告)号：US09400858B1

公开(公告)日：2016-07-26

申请号：US14505414

申请日：2014-10-02

Applicant: Cadence Design Systems, Inc.

Inventor： Tsair-Chin Lin ,  Jingbo Gao ,  Yevgen Ryazanov

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5009 ,  G06F17/5022

Abstract: Essential information for system operations, memory analysis, and design signal analysis is captured while a hardware based verification platform is performing emulation and testing. This recorded information is then accessible via a memory device and can be used to perform offline debugging with a virtual verification machine (VVM). Users can then release the shared resources and run operation commands to control replay of the design test or emulation in offline mode. Users can access any point in time of the recorded emulation in order to perform detailed design analysis and debugging operations. Offline analysis and debugging may include running certain design cycles, rerunning the emulation until the design reaches a certain state, evaluating memory contents in the design, evaluating design signals for any node in the design, etc.

Abstract translation: 在基于硬件的验证平台执行仿真和测试时，捕获系统操作，内存分析和设计信号分析的基本信息。 然后可以通过存储设备访问记录的信息，并且可以使用虚拟验证机（VVM）进行离线调试。 然后，用户可以释放共享资源并运行操作命令来控制离线模式下的设计测试或仿真的重放。 用户可以访问录制仿真的任何时间点，以进行详细的设计分析和调试操作。 离线分析和调试可能包括运行某些设计周期，重新运行仿真直到设计达到某一状态，评估设计中的存储器内容，评估设计中任何节点的设计信号等。

公开(公告)号：US08812286B1

公开(公告)日：2014-08-19

申请号：US13736583

申请日：2013-01-08

Applicant: Cadence Design Systems, Inc.

Inventor： Tsair-Chin Lin ,  Bing Zhu ,  Platon Beletsky

IPC: G06G7/54 ,  G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5022 ,  G06F2217/78

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract translation: 一种用于对集成电路（IC）中的功率管理进行建模的方法包括：指定IC的电路设计和电源架构，所述电源架构包括用于指定所述IC的不同部分中的功率电平的多个功率域; 通过包括用于对仿真模块中的电力架构进行建模的一个或多个硬件元件来确定IC的仿真模块; 以及使用所述仿真模块来模拟所述IC的一个或多个功率域中的变化功率水平，包括在至少一个功率域中的功率切断。