公开(公告)号：US09063831B1

公开(公告)日：2015-06-23

申请号：US13724318

申请日：2012-12-21

Applicant: Cadence Design Systems, Inc.

Inventor： Barton L. Quayle

IPC: G06F12/02 ,  G06F12/00 ,  G06F17/50 ,  G06F11/26

CPC classification number: G06F12/02 ,  G06F11/261 ,  G06F11/263 ,  G06F17/5027

Abstract: The present patent document relates to a method and apparatus for optimizing access to control registers in an emulation chip. Control messages include in one half of the message a write-mask bits for the corresponding control bits in the other half of the word. A single message from the host workstation can be used to update several bits of the register using a single message, rather than reading, modifying, then writing back each bit individually. Only the bits desired to be updated are written, while the masked bits are not affected. Various configurations of the mask bits and control bits are possible, and block transfers can be used to update bits across a series of registers. The disclosed method and apparatus can reduce overhead and latency on communication channels to the host workstation by significantly reducing the number of individual transfer across the channel.

Abstract translation: 本专利文献涉及用于优化对仿真芯片中的控制寄存器的访问的方法和装置。 控制消息在消息的一半中包含用于该字的另一半中的对应控制位的写掩码位。 可以使用来自主机工作站的单个消息来使用单个消息来更新寄存器的几个位，而不是单独读取，修改，然后单独写入每个位。 只有希望更新的位被写入，而掩码位不受影响。 掩码位和控制位的各种配置是可能的，并且块传输可用于更新一系列寄存器中的位。 所公开的方法和装置可以通过显着地减少通过信道的单个传输的数量来减少通向主机工作站的通信信道的开销和等待时间。

公开(公告)号：US09367656B1

公开(公告)日：2016-06-14

申请号：US13717172

申请日：2012-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Barton L. Quayle

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5027 ,  G06F2217/84

Abstract: Clock distribution schemes in emulation systems are typically complex and use significant resources. The present disclosure is generally directed to clock distribution to emulation chips using a serial interconnect mesh. A clock distribution tree is overlayed on the emulation chips allocated to a user's circuit design, the tree branching from a root emulation chip using selected serial interconnections and covering each allocated emulation chip. The emulation chips can recover a clock from received serial signals. The delay associated with each interconnection is determined and used by configuration software when creating the distribution tree. To start emulation stepping synchronously, each emulation chip is configured to know its delay from the root emulation chip. A message is sent from the root emulation chip to each branch emulation chip triggering a timer to countdown a time until emulation is to begin, allowing the emulation chips to start stepping in lockstep.

Abstract translation: 仿真系统中的时钟分配方案通常是复杂的并且使用重要的资源。 本公开通常涉及使用串行互连网络对仿真芯片的时钟分配。 时钟分配树覆盖在分配给用户电路设计的仿真芯片上，该树从使用所选串行互连的根仿真芯片分支并覆盖每个分配的仿真芯片。 仿真芯片可以从接收到的串行信号中恢复时钟。 每个互连相关的延迟在创建分发树时由配置软件确定和使用。 为了同步地开始仿真步骤，每个仿真芯片被配置为知道其从根仿真芯片的延迟。 从根仿真芯片发送到每个分支仿真芯片的消息触发定时器倒计时直到仿真开始，允许仿真芯片开始步进锁定。

公开(公告)号：US09702933B1

公开(公告)日：2017-07-11

申请号：US14920777

申请日：2015-10-22

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Charles R. Berghorn ,  Barton L. Quayle ,  Mitchell G. Poplack

IPC: G06F17/50 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G06F17/5027

Abstract: Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip receiving the encoded word to determine whether the data word was received without error. In another embodiment, test patters may be transmitted along the unused interconnections while the functional verification system implements a hardware design in other interconnections. In another embodiment, a dedicated pattern generator generates test patterns to transmit across the interconnection. During clock cycles in which the interconnection is not used to implement the hardware design, a multiplexer transmits the test pattern across the interconnection.