公开(公告)号：US09702933B1

公开(公告)日：2017-07-11

申请号：US14920777

申请日：2015-10-22

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Charles R. Berghorn ,  Barton L. Quayle ,  Mitchell G. Poplack

IPC: G06F17/50 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G06F17/5027

Abstract: Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip receiving the encoded word to determine whether the data word was received without error. In another embodiment, test patters may be transmitted along the unused interconnections while the functional verification system implements a hardware design in other interconnections. In another embodiment, a dedicated pattern generator generates test patterns to transmit across the interconnection. During clock cycles in which the interconnection is not used to implement the hardware design, a multiplexer transmits the test pattern across the interconnection.

公开(公告)号：US09904759B1

公开(公告)日：2018-02-27

申请号：US15617252

申请日：2017-06-08

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sundar Rajan ,  Charles R. Berghorn ,  Mitchell G. Poplack

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G01R31/317 ,  G06F9/455 ,  G06F17/5027 ,  G06F17/5054

Abstract: A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the testing process. The system further comprises multiple paths to a target pod. The paths enable monitoring and reporting on the status of target connections between an emulator and a target system.

公开(公告)号：US09697324B1

公开(公告)日：2017-07-04

申请号：US14933677

申请日：2015-11-05

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sundar Rajan ,  Charles R. Berghorn ,  Mitchell G. Poplack

IPC: G06F17/50 ,  G06F9/455 ,  G01R31/317

CPC classification number: G06F17/5081 ,  G01R31/317 ,  G06F9/455 ,  G06F17/5027 ,  G06F17/5054

Abstract: A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the testing process. The system further comprises multiple paths to a target pod. The paths enable monitoring and reporting on the status of target connections between an emulator and a target system.