公开(公告)号：US11573883B1

公开(公告)日：2023-02-07

申请号：US16219860

申请日：2018-12-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Aruna Aluri ,  Linwei Ding

IPC: G06F11/34 ,  G06F30/20 ,  G01R31/3183 ,  H03M7/30

Abstract: A trace subsystem of an emulation system may generate differential frame data based upon successive frames. If one compression mode, the trace subsystem may set a flag bit and store differential frame data if there is at least one non-zero bit in the differential frame data. If the differential frame data includes only zero bits, the trace subsystem may set the flag bit without storing the frame data. In another compression mode, the computer may further compress the differential data if the frame data includes one (one-hot) or two (two-hot) non-zero bits. The controller may set flag bits to indicate one of all-zeroes, one-hot, two-hot, and random data conditions (more than two non-zero bits). For one-hot or two-hot conditions, the controller may store bits indicating the positions of the non-zero bits. For random data conditions, the controller may store the entire differential frame.

公开(公告)号：US11520531B1

公开(公告)日：2022-12-06

申请号：US17139163

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Justin Schmelzer ,  Aruna Aluri

IPC: G06F3/06 ,  G06F11/34

Abstract: A system may include a synchronization device and an emulation chip including a processor and a memory. The processor may evaluate, during a first cycle, at least one of a set of one or more execution instructions in the memory or evaluation primitives configured to emulate a circuit, and evaluate, during a second cycle, at least one of the set of one or more execution instructions or a set of configured logic primitives. The synchronization device may interpose a gap period interposed between the first cycle and the second cycle such that during the gap period, the processor does not evaluate one or more instructions from the set of one or more execution instructions or re-evaluate primitives. The synchronization device may cause, during the first gap period, the emulation chip to perform refreshes on the memory of the emulation chip.

公开(公告)号：US11275598B1

公开(公告)日：2022-03-15

申请号：US16208447

申请日：2018-12-03

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Yuhei Hayashi

IPC: G06F9/455 ,  H04L49/101 ,  H04L45/00 ,  G06F13/10 ,  G06F13/38

Abstract: The embodiments disclosed herein describe a switching ASIC that provides a dynamic single-bit routing and multiplexing function in an emulation system. The switching ASIC may receive a set of incoming data streams from a first set of emulation devices (e.g., emulation ASICs), disassemble each data stream to the constituent bits, dynamically multiplex the bits, reassemble the multiplexed bits into outgoing data streams, and transmit the outgoing data streams to a second set of emulation devices. Multiple statically scheduled selection tables (UCSWs), one for each output lane of the switching ASIC, drive the selection and routing of bits from input slots of various input lanes to the output slots of the output lane.

公开(公告)号：US09647688B1

公开(公告)日：2017-05-09

申请号：US14578100

申请日：2014-12-19

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Simon Sabato

IPC: H03M13/00 ,  H03M13/03

CPC classification number: H03M13/03 ,  H03M13/31

Abstract: A method of encoding a data word in a physical coding sublayer before serial transmission is provided, where data words comprising data bits are received, and the data words encoded using one or more 8B/10B encodings to generate 8B/10B transmission characters. ECC check bits are then generated, and the transmission characters and ECC check bits DC balanced prior to shuffling the bits together to form an encoded word to be transmitted. A receiver may decode by implementing a decode process with error correction. In some embodiments 26 data bits from two 13-bit word are encoded into a 40-bit encoded word. Bits of two or more encoded words may be interleaved for transmission, or multiple copies of encoded words sent. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may also implement the disclosed encoding/decoding for interconnections between emulation chips.

公开(公告)号：US09171111B1

公开(公告)日：2015-10-27

申请号：US14500913

申请日：2014-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F2217/68 ,  G06F2217/86

Abstract: A processor-based hardware functional verification system with time shift registers is described. The system includes a processor cluster with a plurality of processors that each have a data inputs and select inputs. Furthermore, a plurality of electronic memories each having a plurality of read ports is associated with the processors, respectively. The time shift registers each have an input in communication with the read ports of the electronic memories and an output in communication with the select inputs of the processors. The system further includes an instruction memory that provides a control signal to each of the time shift registers to store data output from read ports of the electronic memories that can be provided to the processor for evaluation during a subsequent emulation step.

Abstract translation: 描述了具有时移寄存器的基于处理器的硬件功能验证系统。 该系统包括具有多个处理器的处理器集群，每个处理器具有数据输入和选择输入。 此外，分别具有多个读取端口的多个电子存储器与处理器相关联。 时移寄存器各自具有与电子存储器的读取端口通信的输入和与处理器的选择输入通信的输出。 该系统还包括指令存储器，其向每个时移寄存器提供控制信号，以存储从可以提供给处理器的电子存储器的读端口输出的数据，用于在随后的仿真步骤期间进行评估。

公开(公告)号：US11461522B1

公开(公告)日：2022-10-04

申请号：US16212429

申请日：2018-12-06

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Yuhei Hayashi

IPC: G06F30/331 ,  G06F30/34 ,  G06F11/26 ,  G01R31/3183 ,  G06F30/39 ,  G01R31/3177

Abstract: An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

公开(公告)号：US11366950B1

公开(公告)日：2022-06-21

申请号：US17148941

申请日：2021-01-14

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Tarik Hanai Omar ,  TheHung Luu ,  Zaid Khan ,  Jerome Albert

IPC: G06F30/394 ,  G06F111/04 ,  G06F111/02 ,  G06F119/12

Abstract: Methods and systems herein can efficiently interconnect processors through a custom grid (a data mesh) utilizing upper metal layer routing in a semiconductor die design to minimize latency. A computer-implemented method of routing interconnects on a semiconductor die includes receiving a set of non-default routes and associated routing rules; identifying a set of critical signals for feedthrough on the set of non-default routes; generating a connectivity matrix including a set of resulting routes, the resulting routes routing the set of critical signals through the set of non-default routes; generating a timing analysis of the connectivity matrix based on a set of latency requirements; responsive to determining that the timing analysis is not compliant with the latency requirements, generating a set of routing constraints; and updating the associated routing rules to include the set of routing constraints.

公开(公告)号：US11048843B1

公开(公告)日：2021-06-29

申请号：US16217434

申请日：2018-12-12

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Yuhei Hayashi

IPC: G06F30/331 ,  G06F30/327

Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.

公开(公告)号：US09702933B1

公开(公告)日：2017-07-11

申请号：US14920777

申请日：2015-10-22

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Charles R. Berghorn ,  Barton L. Quayle ,  Mitchell G. Poplack

IPC: G06F17/50 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G06F17/5027

Abstract: Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip receiving the encoded word to determine whether the data word was received without error. In another embodiment, test patters may be transmitted along the unused interconnections while the functional verification system implements a hardware design in other interconnections. In another embodiment, a dedicated pattern generator generates test patterns to transmit across the interconnection. During clock cycles in which the interconnection is not used to implement the hardware design, a multiplexer transmits the test pattern across the interconnection.

公开(公告)号：US09372947B1

公开(公告)日：2016-06-21

申请号：US14500899

申请日：2014-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F2217/68 ,  G06F2217/86

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

Abstract translation: 本专利文献涉及一种在仿真电路设计期间压缩由仿真处理器产生的跟踪数据的方法，以及压缩跟踪数据的硬件功能验证系统。 仿真处理器集群内的压缩逻辑累积从仿真处理器输出的数据位，并根据压缩方案，根据使能位识别有效跟踪数据将它们压缩成寄存器中的跟踪数据字节。 根据压缩层级，跟踪数据字节进一步累积并压缩成仿真芯片的较高级处理器集群中较大的跟踪数据字节，压缩的跟踪数据字节存储在仿真芯片的跟踪阵列中。