公开(公告)号：US11610040B1

公开(公告)日：2023-03-21

申请号：US16209597

申请日：2018-12-04

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Barton Quayle ,  Mitchell G. Poplack

IPC: G06F30/30 ,  G06F30/331 ,  G06F30/34 ,  G06F30/333

Abstract: Embodiments disclosed herein describe switching logic in board-level interconnects and in the system-level interconnects that may provide bitwise dynamic routing and switching between corresponding board-level and system-level components. At board-level, a switching ASIC may receive input data through a backplane from an emulation ASIC in a first logic board and route any bit of the input data to any of the emulation ASIC in a second logic board. At system-level, a switching logic board containing a set of switching ASICs may be associated with a logic cluster and may dynamically route data bits from the emulation ASICs in the logic cluster to emulation ASICs to other logic clusters of the emulation system and/or target systems. Additionally, the switching logic board may dynamically route bits from the other logic clusters to the associated logic cluster.

公开(公告)号：US10198538B1

公开(公告)日：2019-02-05

申请号：US14981270

申请日：2015-12-28

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Barton Quayle ,  Mitchell G. Poplack ,  Sundar Rajan ,  Chuck Berghorn

IPC: G06F17/50 ,  G06F15/173 ,  H03M1/66

Abstract: The embodiments described herein may improve utilization of an emulator system's resources, and may improve efficiency and effectiveness in bug-identification and/or target-debugging; the components described herein may improve utilization of the emulator's resources, reduce wait time to execute emulation routines, and may limit or eliminate the need to stop or kill emulations in process. The various embodiments described herein allow for dynamically associating domains and targets by dynamically allocating and assigning domains with particular target connections, which are pins and/or wires that connect target pods to the emulation system. An emulation system may comprise one or more target MUXs that are situated between the target connections and the domains, to allow the relationships between target pods and domains to be identified and switched dynamically. The target MUXs may be reprogrammed while emulations are ongoing, in order to redirect data communications between available domains and target pods of target systems.