公开(公告)号：US10198538B1

公开(公告)日：2019-02-05

申请号：US14981270

申请日：2015-12-28

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Barton Quayle ,  Mitchell G. Poplack ,  Sundar Rajan ,  Chuck Berghorn

IPC: G06F17/50 ,  G06F15/173 ,  H03M1/66

Abstract: The embodiments described herein may improve utilization of an emulator system's resources, and may improve efficiency and effectiveness in bug-identification and/or target-debugging; the components described herein may improve utilization of the emulator's resources, reduce wait time to execute emulation routines, and may limit or eliminate the need to stop or kill emulations in process. The various embodiments described herein allow for dynamically associating domains and targets by dynamically allocating and assigning domains with particular target connections, which are pins and/or wires that connect target pods to the emulation system. An emulation system may comprise one or more target MUXs that are situated between the target connections and the domains, to allow the relationships between target pods and domains to be identified and switched dynamically. The target MUXs may be reprogrammed while emulations are ongoing, in order to redirect data communications between available domains and target pods of target systems.

公开(公告)号：US09904759B1

公开(公告)日：2018-02-27

申请号：US15617252

申请日：2017-06-08

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sundar Rajan ,  Charles R. Berghorn ,  Mitchell G. Poplack

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G01R31/317 ,  G06F9/455 ,  G06F17/5027 ,  G06F17/5054

Abstract: A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the testing process. The system further comprises multiple paths to a target pod. The paths enable monitoring and reporting on the status of target connections between an emulator and a target system.

公开(公告)号：US09697324B1

公开(公告)日：2017-07-04

申请号：US14933677

申请日：2015-11-05

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sundar Rajan ,  Charles R. Berghorn ,  Mitchell G. Poplack

IPC: G06F17/50 ,  G06F9/455 ,  G01R31/317

CPC classification number: G06F17/5081 ,  G01R31/317 ,  G06F9/455 ,  G06F17/5027 ,  G06F17/5054

Abstract: A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the testing process. The system further comprises multiple paths to a target pod. The paths enable monitoring and reporting on the status of target connections between an emulator and a target system.