公开(公告)号：US11308008B1

公开(公告)日：2022-04-19

申请号：US17139333

申请日：2020-12-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Christian Wiencke ,  Bhoumik Shah ,  Ping-Sheng Tseng

IPC: G06F13/16 ,  G06F9/455 ,  G06F13/28

Abstract: Embodiments described herein provide for an emulation system that supports efficiently generating outgoing messages to a test bench. The emulation system transmits the outgoing messages to the test bench various busses and interfaces. The compiled virtual logic writes the outgoing messages into memories of the emulation chips for queuing, and notification messages associated with the queued outgoing messages. A traffic processor transfers from memories to the test bench using buses and interfaces. The traffic processor reads a notification message from memory to identify the storage location with a corresponding queued outgoing message. The traffic processor then transmits DMA requests to I/O components (e.g., DMA engines) to instruct the I/O components to transfer the queued outgoing message to the host device.