公开(公告)号：US09400311B1

公开(公告)日：2016-07-26

申请号：US14675365

申请日：2015-03-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Anil Malik ,  Sameer Chakravarthy Chillarige ,  Sharjinder Singh ,  Joseph Swenton ,  Gilbert Vandling

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/318342 ,  G01R31/31703

Abstract: In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.

Abstract translation: 为了检测和定位共享共同设计的多个芯片或其他电路中的缺陷或故障，每个芯片都响应于输入而被测试不正确的输出或失败。 然后通过在芯片设计的仿真芯片上模拟一系列可疑故障候选，然后将每个故障候选产生的不正确输出与各个芯片的不正确输出进行比较，确定不正确的输出在单个仿真中进行统一诊断，以确定 如果故障候选者产生芯片的所有故障，而不产生其他故障。 测试输入和预期输出可以通过自动测试模式生成来预先确定。 故障候选可以通过使用诸如后锥跟踪的回溯处理来确定。 可能与测量点，导致故障的输入模式和故障值相关联地记录故障。