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公开(公告)号：US12019118B2
公开(公告)日：2024-06-25
申请号：US18186549
申请日：2023-03-20
IPC分类号： G01R31/317
CPC分类号： G01R31/31703 , G01R31/31722
摘要： In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.
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公开(公告)号：US12019117B2
公开(公告)日：2024-06-25
申请号：US17888491
申请日：2022-08-16
发明人： Kai Lei , Yikai Liang , Yudan Deng , Linglan Zhang , Jinfu Ye , Huan Liu
IPC分类号： H03M1/66 , G01R31/317 , G01R31/3187
CPC分类号： G01R31/31703 , G01R31/3187
摘要： A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.
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公开(公告)号：US20240142518A1
公开(公告)日：2024-05-02
申请号：US18500337
申请日：2023-11-02
申请人： SiFive, Inc.
发明人： Cameron Mcnairy
IPC分类号： G01R31/317
CPC分类号： G01R31/31703 , G01R31/31726
摘要： A first circuitry may be configured to generate a first output based on an input and send an indication responsive to detection of an error while the first output is generated. A second circuitry may be configured to generate a second output based on the input. A wrapper circuitry may be configured to compare the first output and the second output to check correctness by default, and responsive to receipt of the indication, select the second output as a system output without checking for correctness by comparing the first output and the second output. In some implementations, the second circuitry may be configured to send a second indication responsive to detection of a second error while the second output is generated. The wrapper circuitry may be configured to, responsive to receipt of the second indication, ignore the check for correctness.
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公开(公告)号：US11934094B2
公开(公告)日：2024-03-19
申请号：US17301032
申请日：2021-03-23
发明人： Effendi Leobandung , Stephen Wu
IPC分类号： G06F30/32 , G01N21/95 , G01R31/317 , G03F1/44
CPC分类号： G03F1/44 , G01N21/9501 , G01R31/31703 , G06F30/32
摘要： According to a first aspect of the present invention, there is provided a method, a computer system and a computer program product. The method, computer system and computer program product including measuring an initial state of a set of SRAM bits on the wafer, identifying a first set of signature SRAM bits on the wafer, of the set of SRAM bits on the wafer, where the first set of SRAM bits comprise a consistent initial state greater than a first threshold percentage of times, measuring physically dimensions of features of the first set of SRAM bits on the wafer; and identifying a set of signature SRAM bits of the first set of SRAM bits on the wafer, wherein the set of signature SRAM bits comprise physical dimensions of features which correlate to the initial state of each correlated SRAM bit.
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公开(公告)号：US11927631B2
公开(公告)日：2024-03-12
申请号：US17777561
申请日：2020-05-06
发明人： Shanzhi Chen , Guobin Su , Yun Yang
IPC分类号： G01R31/3183 , G01R31/3167 , G01R31/317 , G01R31/3181 , G01R31/319 , G06F11/20 , G06F11/263 , G11C29/10 , H04B17/29 , H04L1/24
CPC分类号： G01R31/31835 , G01R31/3167 , G01R31/31703 , G01R31/31813 , G01R31/3183 , G01R31/318385 , G01R31/31908 , G06F11/2038 , G06F11/263 , G11C29/10 , H04B17/29 , H04L1/24 , H04L1/242 , H04L1/244
摘要： Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.
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公开(公告)号：US11888654B2
公开(公告)日：2024-01-30
申请号：US17898851
申请日：2022-08-30
发明人： Jueon Kim , Taehyoung Kim , Seungjin Park , Jihwan Hyun , Myoungbo Kwak , Junghwan Choi
CPC分类号： H04L25/03006 , G01R31/31703 , H03K5/24 , H03K9/02 , H03K21/08 , H04B17/21 , H04L27/06
摘要： An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.
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公开(公告)号：US11808809B2
公开(公告)日：2023-11-07
申请号：US16961229
申请日：2018-11-23
申请人： Robert Bosch GmbH
发明人： Carsten Hermann
IPC分类号： G01R31/3167 , G01R31/317
CPC分类号： G01R31/3167 , G01R31/3172 , G01R31/31701 , G01R31/31703
摘要： An electrical circuit for testing primary internal signals of an ASIC. Only test pin is provided via which a selection can be made of a digital or analog signal to be observed. The electrical circuit includes a Schmitt trigger between the test pin and an output terminal of the electrical circuit. A test mode id activated when a switching threshold of the Schmitt trigger is exceeded. At least one sub-circuit is provided for the observation of a digital signal, having a resistor, an NMOS transistor, and an AND gate, at whose first input the digital signal is present. The resistor is between the test pin and the drain terminal of the NMOS transistor. The source terminal is connected to ground, and the gate terminal is connected to the output of the AND gate. The second input of the AND gate being connected to the output terminal of the electrical circuit.
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公开(公告)号：US20230280397A1
公开(公告)日：2023-09-07
申请号：US17732551
申请日：2022-04-29
发明人： Chuanzhen OU , Yanlin Xie , Yanwei Wang
IPC分类号： G01R31/317
CPC分类号： G01R31/31708 , G01R31/31703
摘要： The present disclosure discloses an oscillation handling method, an apparatus using the same, and a storage medium. The method includes: obtaining one of a real-time detection voltage and a real-time power of an oscillation system; reducing a gain of the system according to a preset first attenuation value; determining whether the real-time detection voltage meets a first oscillation determination condition; if yes, increase an oscillation determination number by one; restoring the gain of the system to obtain the second real-time detection voltage; determining whether the second real-time detection voltage meets a second oscillation determination condition; if yes, increase the oscillation determination number by two and reduce the gain of the system according to the preset first attenuation value; and determining the preset first attenuation value as a determined oscillation attenuation value in response to the oscillation determination number being larger than or equal to a preset threshold.
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公开(公告)号：US20230236244A1
公开(公告)日：2023-07-27
申请号：US17582207
申请日：2022-01-24
申请人： Quantum Machines
发明人： Avishai Zvi , Ori Weber , Nissim Ofek
IPC分类号： G01R31/317 , G06N10/20 , G06N10/60
CPC分类号： G01R31/31703 , G06N10/20 , G06N10/60 , G01R31/31712
摘要： In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.
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公开(公告)号：US20230213578A1
公开(公告)日：2023-07-06
申请号：US18089764
申请日：2022-12-28
IPC分类号： G01R31/317 , G01R31/3173
CPC分类号： G01R31/31703 , G01R31/31725 , G01R31/3173
摘要： A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.
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