公开(公告)号：US09405882B1

公开(公告)日：2016-08-02

申请号：US14752206

申请日：2015-06-26

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Amit Dhuria ,  Naresh Kumar ,  Prashant Sethia ,  Jeannette Sutherland ,  Shashank Tripathi

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/84

Abstract: A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.

Abstract translation: 一种用于集成电路设计的输入/输出模式的静态时序分析方法，其包括以硬件描述语言描述的集成电路设计加载到存储器中。 定义了静态时序分析的活动区域，其包括输入/​​输出端口与输入端口上游和输出端口下游的顺序逻辑元件的选定级别之间的逻辑和互连。 使用硬件描述语言生成活动区域的描述。 然后对活动区域的逻辑执行静态时序分析。

公开(公告)号：US10114920B1

公开(公告)日：2018-10-30

申请号：US15197142

申请日：2016-06-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Umesh Gupta ,  Shashank Tripathi ,  Naresh Kumar ,  Arvind Nembili Veeravalli ,  Prashant Sethia ,  Ritika Govila

IPC: G06F17/50

Abstract: A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.