公开(公告)号：US11003821B1

公开(公告)日：2021-05-11

申请号：US16798260

申请日：2020-02-21

Applicant: Cadence Design Systems, Inc.

Inventor： Sri Harsha Pothukuchi ,  Amit Dhuria

IPC: G06F30/3315 ,  G06F30/333 ,  G06F111/04 ,  G06F119/12

Abstract: The present embodiments relate to static timing analysis (STA) of circuits. The STA can be carried out concurrently for multiple-mode-multiple-corners (MMMC) for circuits including combinational loops. The STA includes determining hard breaking points in the loop associated with each single-mode-single-corner (SMSC) view. The STA also includes merging constraints of all SMSC views to generate a merged set of constraints. The STA includes running MMMC STA for the circuit based on the merged set of constraints. The STA also includes determining a soft breaking point for the loop in the MMMC view for timing propagation and settling. The STA maintains consistency of breaking points across SMSC and MMMC views.

公开(公告)号：US10133842B1

公开(公告)日：2018-11-20

申请号：US15133665

申请日：2016-04-20

Applicant: Cadence Design Systems, Inc.

Inventor： Pawan Kulshreshtha ,  Amit Dhuria ,  Krishna Prasad Belkhale ,  Saulius Kersulis

IPC: G06F17/50

Abstract: Disclosed are techniques for multi-mode, multi-corner physical optimization of electronic designs. These techniques identify an electronic design and a global set of views. Timing information is characterized with the global set of views for the electronic design. A set of active views is generated at least by pruning one or more views from the global set of views for a first node in the electronic design while maintaining the one or more views for a second node in the set of active views. The electronic design is then associated with the set of active views that is stored in a data structure in a non-transitory computer accessible storage medium.

公开(公告)号：US11188696B1

公开(公告)日：2021-11-30

申请号：US16384815

申请日：2019-04-15

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Sri Harsha Venkata Pothukuchi ,  Pradeep Yadav ,  Pawan Kulshreshtha ,  Igor Keller ,  Sharad Mehrotra ,  Jean Pierre Hiol ,  Krishna Prasad Belkhale

IPC: G06F30/30 ,  G06F30/3312 ,  G06F16/901 ,  G06F17/18

Abstract: An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.

公开(公告)号：US10990733B1

公开(公告)日：2021-04-27

申请号：US16814928

申请日：2020-03-10

Applicant: Cadence Design Systems, Inc.

Inventor： Vibhor Garg ,  Amit Dhuria

IPC: G06F30/3315 ,  G06F119/12

Abstract: According to certain aspects, the present embodiments include techniques for performing a single timing analysis run for a plurality of views representing different modes and/or corners. An embodiment analyzes and maintains relevant timing information that is different for different views, but otherwise maintains the same information for all views. This allows each individual view in a single run to be analyzed in the same manner as separate runs for each separate view, thereby ensuring the same QoR. These and other embodiments provide substantial savings in runtime and memory consumption over other approaches.

公开(公告)号：US08863052B1

公开(公告)日：2014-10-14

申请号：US13940576

申请日：2013-07-12

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Naresh Kumar ,  Umesh Gupta ,  Pradeep Yadav ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.

Abstract translation: 提供了一种用于产生用于预定电路设计的操作的结构感知定时模型的系统和方法。 产生定时模型以具有表示电路设计的定时特性的多个定时弧。 另外，评估电路设计的端子对以确定通过电路设计的所选路径的特征结构权重。 结构感知定时模型然后可以被并入到顶级分级电路设计中，用于定时分析和悲观消除以达到实际的定时特性。 结构重量在AOCV型悲观消除后期处理中特别有用。

公开(公告)号：US11144698B1

公开(公告)日：2021-10-12

申请号：US16946677

申请日：2020-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vibhor Garg ,  Edward J. Martinage ,  Amit Dhuria ,  Krishna Prasad Belkhale

IPC: G06F30/392 ,  G06F30/396 ,  G06F30/31 ,  G06F30/327 ,  G06F111/12

Abstract: An approach is described for a method, system, and product, that includes identification/generation of a synthesized netlist for use in optimization and placement, generation and utilization of multiple uncertainty values for an early clock tree for guiding optimization and placed of circuit elements in a placeopt process that operates on a path by path basis. In some embodiments, the approach further comprises execution of clock tree synthesis, and routing the synthesized clock tree. In some embodiments, uncertainty values are propagated along data paths where each data path is associated with an uncertainty value, and where each path is optimized and placed on a path my path basis in order to meeting timing requirements and one or more design goals.

公开(公告)号：US09405882B1

公开(公告)日：2016-08-02

申请号：US14752206

申请日：2015-06-26

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Amit Dhuria ,  Naresh Kumar ,  Prashant Sethia ,  Jeannette Sutherland ,  Shashank Tripathi

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/84

Abstract: A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.

Abstract translation: 一种用于集成电路设计的输入/输出模式的静态时序分析方法，其包括以硬件描述语言描述的集成电路设计加载到存储器中。 定义了静态时序分析的活动区域，其包括输入/​​输出端口与输入端口上游和输出端口下游的顺序逻辑元件的选定级别之间的逻辑和互连。 使用硬件描述语言生成活动区域的描述。 然后对活动区域的逻辑执行静态时序分析。

公开(公告)号：US08788995B1

公开(公告)日：2014-07-22

申请号：US13842178

申请日：2013-03-15

Applicant: Cadence Design Systems, Inc.

Inventor： Naresh Kumar ,  Prashant Sethia ,  Amit Dhuria ,  Krishna Belkhale

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.

Abstract translation: 提供了一种系统和方法，用于减少为电路设计的优化提供的定时数据库的悲观情绪。 通过生成基于混合图的静态时序分析（GBA）和基于路径的静态时序分析（PBA STA）数据库来减少悲观。 选择性地对最关键的GBA识别的定时违规执行PBA，目的是减少传递到物理实现校正优化器模块的操作时序特性的错误悲观，从而减少电路设计上的不必要的固定和转换，从而相应地减少设计时间 存储空间，所需的处理能力用于定时关闭，并且导致完成的可操作和有形的电路装置，其面积减小，功率要求低，成本降低。

公开(公告)号：US10169501B1

公开(公告)日：2019-01-01

申请号：US15182353

申请日：2016-06-14

Applicant: Cadence Design Systems, Inc.

Inventor： Pawan Kulshreshtha ,  Amit Dhuria

IPC: G06F17/50

Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

公开(公告)号：US10037394B1

公开(公告)日：2018-07-31

申请号：US15182338

申请日：2016-06-14

Applicant: Cadence Design Systems, Inc.

Inventor： Pawan Kulshreshtha ,  Amit Dhuria

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5045 ,  G06F2217/84

Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.