MASK AND MANUFACTURING METHOD THEREFOR

    公开(公告)号:US20220216412A1

    公开(公告)日:2022-07-07

    申请号:US17607012

    申请日:2020-12-24

    摘要: A mask includes a frame, at least one mask sheet, and a shielding plate. The frame includes a plurality of borders. The borders are connected end to end in sequence to form the frame with a first hollow region. A mask sheet includes a pattern region and non-pattern regions. The pattern region includes at least one evaporation hole. The shielding plate includes a plurality of shielding strips. The plurality of shielding strips are arranged crosswise to form a plurality of second hollow regions. Orthogonal projections of the second hollow regions on a plane perpendicular to a thickness direction of the frame are located within a range of an orthogonal projection of the first hollow region on the plane. An inner edge of an orthogonal projection of the frame on the plane is located within a range of an orthogonal projection of the shielding plate on the plane.

    MANUFACTURING METHOD OF ARRAY SUBSTRATE
    4.
    发明申请
    MANUFACTURING METHOD OF ARRAY SUBSTRATE 有权
    阵列基板的制造方法

    公开(公告)号:US20150332979A1

    公开(公告)日:2015-11-19

    申请号:US14127264

    申请日:2012-11-09

    IPC分类号: H01L21/66 H01L27/12

    摘要: An embodiment of the present invention provides a manufacturing method of an array substrate comprising forming a gate detecting pattern on the array substrate with gate lines and common electrode lines formed thereon, the gate detecting pattern being arranged on one side of a pixel region of the array substrate and used to connect all the common electrode lines for pixel units; and performing a short circuit or a open circuit detection, wherein if the difference between a signal received by a receiving terminal for a gate line and a signal transmitted from a transmitting terminal for the gate line is larger than a predetermined detection threshold value, it is determined that short circuit between the gate line and a common electrode line or open circuit in the gate line occurs.

    摘要翻译: 本发明的实施例提供一种阵列基板的制造方法,包括在阵列基板上形成栅极线和形成在其上的公共电极线的栅极检测图案,栅极检测图案布置在阵列的像素区域的一侧 用于连接像素单元的所有公共电极线; 以及执行短路或开路检测,其中如果由栅极线的接收端接收的信号与从栅极线的发送端发送的信号之间的差大于预定的检测阈值,则为 确定栅极线与公共电极线之间的短路或栅极线中的开路发生。