公开(公告)号：US20210167557A1

公开(公告)日：2021-06-03

申请号：US16952860

申请日：2020-11-19

Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

Inventor： John Bruce BOWLERWELL ,  John Anthony BRESLIN

IPC: H01R13/66 ,  H01R13/641 ,  H01R24/58 ,  G01R31/69

Abstract: The present disclosure relates to circuitry for detecting at least partial removal of an audio accessory plug from a corresponding socket. The circuitry comprises a monitoring unit comprising a first terminal configured to be electrically connected to a first socket contact of the socket that is in electrical contact with a first plug contact of the plug when the plug is fully received in the socket. The monitoring unit is configured to monitor a first impedance of a first signal path coupled to the first terminal, and the circuitry is configured to output a signal indicative of detection of at least partial removal of the plug from the socket in response to detection by the monitoring unit of a first predetermined sequence of impedance states of the first signal path.

公开(公告)号：US20210064979A1

公开(公告)日：2021-03-04

申请号：US16554984

申请日：2019-08-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Toru IDO ,  David Paul SINGLETON ,  Gordon James BATES ,  John Anthony BRESLIN

IPC: G06N3/063 ,  H03M1/74

Abstract: This application relates to computing circuitry (200, 500, 600) for analogue computing. A plurality of current generators (201) are each configured to generate a defined current (ID1, ID2, . . . IDj) based on a respective input data value (D1, D2, . . . Dj). A memory array (202), having at least one set (204) of programmable-resistance memory cells (203), is arranged to receive the defined currents from each of the current generators at a respective signal line (206). Each set (204) of programmable-resistance memory cells (203) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module (207) is coupled to each of the signal lines to generate a voltage at an output node (210) based on the sum of the voltages on each of the signal lines.