公开(公告)号：US20210064979A1

公开(公告)日：2021-03-04

申请号：US16554984

申请日：2019-08-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Toru IDO ,  David Paul SINGLETON ,  Gordon James BATES ,  John Anthony BRESLIN

IPC: G06N3/063 ,  H03M1/74

Abstract: This application relates to computing circuitry (200, 500, 600) for analogue computing. A plurality of current generators (201) are each configured to generate a defined current (ID1, ID2, . . . IDj) based on a respective input data value (D1, D2, . . . Dj). A memory array (202), having at least one set (204) of programmable-resistance memory cells (203), is arranged to receive the defined currents from each of the current generators at a respective signal line (206). Each set (204) of programmable-resistance memory cells (203) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module (207) is coupled to each of the signal lines to generate a voltage at an output node (210) based on the sum of the voltages on each of the signal lines.

公开(公告)号：US20180351569A1

公开(公告)日：2018-12-06

申请号：US15991619

申请日：2018-05-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul LESSO ,  David Paul SINGLETON

IPC: H03M1/50 ,  H03M1/08 ,  H03M1/06 ,  H03M1/34

CPC classification number: H03M1/504 ,  H03M1/0604 ,  H03M1/0626 ,  H03M1/0854 ,  H03M1/182 ,  H03M1/34 ,  H03M1/508

Abstract: This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse-width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN).