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公开(公告)号：US20240269706A1
公开(公告)日：2024-08-15
申请号：US18644538
申请日：2024-04-24
Inventor： John Paul LESSO , Toru IDO
IPC: B06B1/02
CPC classification number: B06B1/0261 , B06B2201/55
Abstract: The present disclosure relates to driver circuitry for driving a piezoelectric transducer. The circuitry comprises: a power supply; a reservoir capacitance; switch network circuitry; and control circuitry. The control circuitry is configured to control operation of the switch network circuitry so as to charge the reservoir capacitance from the power supply and to transfer charge between the reservoir capacitance and the piezoelectric transducer.
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公开(公告)号：US20240264112A1
公开(公告)日：2024-08-08
申请号：US18685979
申请日：2022-08-25
Inventor： John Paul LESSO , Toru IDO
IPC: G01N27/327 , G01R19/165
CPC classification number: G01N27/3273 , G01R19/165 , G01R19/16566
Abstract: Circuitry for and methods of analyte measurement Circuitry for measuring a characteristic of an electrochemical cell, the circuitry comprising: a hysteretic comparator having a first comparator input, a second comparator input and a comparator output; a feedback path between the comparator output and the second comparator input configured to provide a feedback signal to the second comparator input; and a loop filter configured to apply filtering to the feedback path to generate the feedback signal, wherein the loop filter comprises the electrochemical cell.
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公开(公告)号：US20220143651A1
公开(公告)日：2022-05-12
申请号：US17092613
申请日：2020-11-09
Inventor： John P. LESSO , Toru IDO
Abstract: The present disclosure relates to circuitry for driving a load. The circuitry comprises driver circuitry configured to generate a drive signal, based on an input signal to the driver circuitry, for driving the load, and commutator circuitry for coupling the driver circuitry to the load. The commutator circuitry is configured to alternate between commutation states in response to a level of the drive signal meeting a drive signal threshold or in response to a level of the input signal meeting a first input signal threshold. The circuitry is configured to apply an offset to the input signal when the input signal is below a second input signal threshold so as to increase a minimum level of the drive signal above the drive signal threshold or to increase a minimum level of the input signal above the first input signal threshold.
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公开(公告)号：US20210367567A1
公开(公告)日：2021-11-25
申请号：US17319620
申请日：2021-05-13
Inventor： John P. LESSO , Toru IDO
IPC: H03F3/217
Abstract: This application describes time-encoding modulator circuitry (200), and in particular a PWM modulator suitable for use for a class-D amplifier. A forward signal path receives a digital input signal (Din) and outputs an output PWM signal (Sout) and includes a first PWM modulator (101). A feedback path provides feedback to an input to of the first PWM modulator (101). The feedback path includes an ADC (203) which receive a first PWM signal (Sa) derived from the output PWM signal. The ADC (203) includes a second PWM modulator (401) which generates a second PWM signal (Sb) based on the first PWM signal. A controller (201) controls the second PWM modulator such that a PWM carrier of the second PWM signal is phase and frequency matched to a PWM carrier of the output PWM signal.
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公开(公告)号：US20210351755A1
公开(公告)日：2021-11-11
申请号：US17386287
申请日：2021-07-27
Inventor： John Paul LESSO , Toru IDO
Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.
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Patent Agency Ranking
公开(公告)号：US20190103862A1
公开(公告)日：2019-04-04
申请号：US15916708
申请日：2018-03-09
Inventor： Toru IDO
Abstract: This application relates to digital PWM modulation. A PWM modulator (400, 1100) has a PWM generator (402) configured to receive pulse width data (PWidth) and to output a PWM signal (SPWM) comprising a plurality of repeating PWM cycle periods, in which the duration of any pulse of the PWM signal in each PWM cycle period is based on the pulse width data. The PWM generator is configured to synchronise the PWM cycle periods, and the start and end of any PWM pulse, to a received first clock signal. The PWM generator is operable to generate pulses that have a positional error from a centred position within the PWM cycle period and a pulse position controller (403) is configured to control the position of a pulse in a PWM cycle period so as to at least partly compensate for the positional error of one or more preceding pulses.
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公开(公告)号：US20170194926A1
公开(公告)日：2017-07-06
申请号：US15466661
申请日：2017-03-22
Inventor： John Paul LESSO , Toru IDO
CPC classification number: H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2175 , H03F2200/102 , H03F2200/339 , H03F2200/432 , H03G7/002 , H03G7/007
Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).
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公开(公告)号：US20240215860A1
公开(公告)日：2024-07-04
申请号：US18406665
申请日：2024-01-08
Inventor： John P. LESSO , Yanto SURYONO , Toru IDO
CPC classification number: A61B5/0823 , A61B5/0803 , A61B5/6803 , A61B5/7246 , A61B5/725 , A61B5/7264 , A61B5/7275 , A61B2562/0219
Abstract: A method of cough detection in a headset, the method comprising: receiving a first signal from an external transducer of the headset; receiving a second signal from an in-ear transducer of the headset; and detecting a cough of a user of the headset based on the first and second signals.
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公开(公告)号：US20230059155A1
公开(公告)日：2023-02-23
申请号：US17880432
申请日：2022-08-03
Inventor： John P. LESSO , Toru IDO
Abstract: Circuitry for balancing cells in a battery pack, the circuitry comprising: cell balancing circuitry configured to transfer energy between cells of the battery pack in synchronisation with a clock signal; and control circuitry configured to control a parameter of the clock signal based on a monitored parameter or information associated with the battery pack.
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公开(公告)号：US20230053745A1
公开(公告)日：2023-02-23
申请号：US17881279
申请日：2022-08-04
Inventor： John P. LESSO , Toru IDO , Anthony S. DOY
Abstract: Balancing circuitry for balancing cells in first and second modules of a battery pack, wherein the first module comprises a first plurality of cells and the second module comprises a second plurality of cells, the balancing circuitry comprising: first cell balancing circuitry operative to balance the first plurality of cells of the first module; and second cell balancing circuitry operative to balance the second plurality of cells of the second module, wherein the second cell balancing circuitry is further operative to balance at least one cell of the first plurality of cells of the first module with at least one cell of the second plurality of cells of the second module.
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