Automatic multi-stage fabric generation for FPGAs

    公开(公告)号:US11509605B1

    公开(公告)日:2022-11-22

    申请号:US17167093

    申请日:2021-02-04

    申请人: Venkat Konda

    发明人: Venkat Konda

    摘要: Systems and methods to automatically or manually generate various multi-stage pyramid network based fabrics, either partially connected or fully connected, are disclosed by changing different parameters of multi-stage pyramid network including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers in any switch, connections between stages of rings either between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of iterations, to route a given set of benchmarks or designs having a specific connection requirements.

    Spraying for unequal link connections in an internal switch fabric

    公开(公告)号:US11316796B2

    公开(公告)日:2022-04-26

    申请号:US16730031

    申请日:2019-12-30

    摘要: In general, techniques are described for facilitating balanced cell handling by fabric cores of a fabric plane for an internal device switch fabric. In some examples, a routing system includes a plurality of fabric endpoints and a switching fabric comprising a fabric plane to switch cells among the fabric endpoints. The fabric plane includes two fabric cores and one or more inter-core links connecting the fabric cores. Each fabric core selects an output port of the fabric core to which to route a received cell of the cells based on (i) an input port of the fabric core on which the received cell was received and (ii) a destination fabric endpoint for the received cell, at least a portion of the selected output ports being connected to the inter-core links, and switches the received cell to the selected output port.

    DEVICE AND METHOD WITH MULTI-STAGE ELECTRICAL INTERCONNECTION NETWORK

    公开(公告)号:US20230412524A1

    公开(公告)日:2023-12-21

    申请号:US18460901

    申请日:2023-09-05

    IPC分类号: H04L49/1515 H04Q3/52

    CPC分类号: H04L49/1515 H04Q3/52

    摘要: A device and method that implements a multi-stage electrical interconnection network is provided. The electronic device includes a plurality of computing devices and a plurality of switches grouped into a plurality of groups. Switches, of the plurality of switches, in a same group are configured to be fully connected to computing devices in the same group, each of switches of the plurality of switches included in a first group among the plurality of groups is configured to have a ono-to-one connection with any one of switches included in a second group, and a connection between the computing devices in the same group and the switches in the same group and a connection between switches in in the plurality of groups are electrical connections.

    Controller and system
    8.
    发明授权

    公开(公告)号:US11437755B2

    公开(公告)日:2022-09-06

    申请号:US16599238

    申请日:2019-10-11

    发明人: Brian R. Wines

    摘要: According to one embodiment, a controller may include a user interface that is operable to receive input from a user to control an electronic system to which the controller may be coupled either directly or indirectly. The user interface may comprise an interface housing to which the user interface is coupled, the interface housing having a front portion and a rear portion, the front portion of which may contain the user interface. A controller housing may be coupled to the rear portion of the interface housing, the controller housing having a smaller perimeter than the interface housing. The controller housing may be comprised of at least one sidewall and a rear wall. At least one magnet may be coupled to the controller housing. The magnet(s) may be operable to hold the controller in position using magnetic force when the controller housing is inserted into a mounting receptacle.

    Fast scheduling and optimization of multi-stage hierarchical networks

    公开(公告)号:US12015566B1

    公开(公告)日:2024-06-18

    申请号:US17878090

    申请日:2022-08-01

    申请人: Venkat Konda

    发明人: Venkat Konda

    CPC分类号: H04L49/1515 H04L49/102

    摘要: Significantly optimized multi-stage networks including scheduling methods for faster scheduling of connections, useful in wide target applications, with VLSI layouts using only horizontal wires and vertical wires to route large scale partial multi-stage hierarchical networks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are disclosed. The optimized multi-stage networks in each block employ one or more slices of rings of stages of switches with inlet and outlet links of partial multi-stage hierarchical networks connecting to rings from either left-hand side or right-hand side; and employ hop wires or multi-drop hop wires wherein hop wires or multi-drop wires are connected from switches of stages of rings of slices of a first partial multi-stage hierarchical network to switches of stages of rings of slices of the first or a second partial multi-stage hierarchical network.