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公开(公告)号：US11769785B2
公开(公告)日：2023-09-26
申请号：US17072460
申请日：2020-10-16
Inventor： Bertrand Chambion , Jean-Philippe Colonna
IPC: H01L27/146
CPC classification number: H01L27/14698 , H01L27/1464 , H01L27/1469 , H01L27/14634 , H01L27/14636
Abstract: A process includes providing electronic chips, the chips having been diced beforehand and each including a stack including a matrix-array of pixels, an interconnect layer, first layer, joining the electronic chips to a carrier substrate, so as to leave a spacing region between the chips; forming a redistribution layer having lateral ends extending into each spacing region; forming metal pillars on the lateral ends; moulding a material including first segments, facing the first layers, second segments which are separate from the first segments, and which extend around the metal pillars; the first and second segments being coplanar; applying a heat treatment, the formed material being chosen so that the stack is curved with a convex shape; the second segments remaining coplanar at the end.
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公开(公告)号：US11424286B2
公开(公告)日：2022-08-23
申请号：US16937752
申请日：2020-07-24
Inventor： Bertrand Chambion , Jean-Philippe Colonna
IPC: H01L27/00 , H01L27/146 , H01L27/15 , H01L31/0392 , H01L31/18 , H01L33/00 , H01L33/58 , H01L33/62
Abstract: A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.
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公开(公告)号：US10658420B2
公开(公告)日：2020-05-19
申请号：US16477925
申请日：2018-01-17
Inventor： Bertrand Chambion , Emmanuel Hugot
IPC: H01L27/146
Abstract: A method for producing a plurality of curved electronic circuits includes: producing a support including a plurality of membranes made from at least one material having a rigidity of more than around 100 MPa, each intended for being part of one of the electronic circuits and having a radius of curvature R between about 15 mm and 500 mm; applying a force to one of the main surfaces of each of the membranes, so that the membrane deforms resiliently and has a substantially planar shape when exposed to the force; rigidly connecting at least one electronic component to each of the membranes; and removing the force applied to one of the main faces of each of the membranes so that each of the membranes retrieves its original radius of curvature R and curves the electronic component according to this radius of curvature R.
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Patent Agency Ranking
公开(公告)号：US11165005B2
公开(公告)日：2021-11-02
申请号：US16342446
申请日：2017-10-16
Inventor： Adrien Gasse , David Henry , Bertrand Chambion
Abstract: The invention relates to a method for producing a first microelectronic chip including a layer of interest having a connection face, intended to be hybridized with a second microelectronic chip. The method including depositing a layer of adhesive on a face of the layer of interest opposite to the first connection face and fastening a handle layer to the layer of adhesive. The method also includes, prior to the steps of depositing the adhesive and fastening the handle layer, defining, on the one hand, a maximum thickness eccmax and a minimum value Eccmin and a maximum value Eccmax of the Young's modulus for the layer of adhesive, and, on the other hand, the minimum thickness ecpmin for the handle layer.
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公开(公告)号：US11289359B2
公开(公告)日：2022-03-29
申请号：US16956377
申请日：2018-12-20
Inventor： Bertrand Chambion
IPC: H01L21/683 , H01L33/00 , H01L25/075 , H01L33/08 , H01L33/24 , H01L33/62
Abstract: A method of manufacturing a device includes: —a) a first step for the formation of a temporary structure that comprises electroluminescent structures separated by trenches and comprising an electroluminescent face, the electroluminescent structures being bonded by means of a bond layer on a temporary substrate; b) an assembly step bringing the electroluminescent structures into contact with a host face of a host substrate; and c) a step for removal of the temporary substrate; wherein the bond layer, that comprises an electrically conducting organic polymer material at least partially transparent to light radiation, is at least partly kept after step c) and forms an electrode common to the light emitting faces, with a thickness of more than 20 nm.
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公开(公告)号：US10991738B2
公开(公告)日：2021-04-27
申请号：US16179355
申请日：2018-11-02
Inventor： Bertrand Chambion , Stephane Caplet
IPC: H01L27/146 , H01L21/683 , H01L21/52 , H01L51/00
Abstract: A method for producing curved electronic circuits is provided, including placing adhesive elements between electronic chips and curved bearing surfaces, with the chips disposed between the surfaces and a flexible film, and such that the chips, the elements, and the surfaces are arranged in a single volume to be depressurised towards an environment outside the volume, the volume including empty spaces between the chips and the surfaces, the spaces being in fluid communication with each other within the volume; establishing a pressure difference between an inside and an outside of the volume such that the film applies a pressure on and collectively deforms the chips in accordance with the surfaces; and stopping the establishing of the pressure difference, the chips being collectively maintained against the surfaces by the elements such that a shape of each of the chips conforms to a corresponding shape of each of the surfaces.
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公开(公告)号：US20210028222A1
公开(公告)日：2021-01-28
申请号：US16937752
申请日：2020-07-24
Inventor： Bertrand Chambion , Jean-Philippe Colonna
IPC: H01L27/146 , H01L31/0392 , H01L31/18 , H01L27/15 , H01L33/00 , H01L33/58 , H01L33/62
Abstract: A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.
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公开(公告)号：US10820407B2
公开(公告)日：2020-10-27
申请号：US16474955
申请日：2017-12-22
Inventor： Bertrand Chambion
Abstract: An electronic structure includes a plurality of electronic devices arranged in the form of a matrix array including a first number of rows, the electronic devices of each row being connected in series, the matrix array further including a plurality of switches, the rows of the matrix array being distributed in a second number of groups intended to be connected in series by the switches, the groups connected in series being supplied with an electrical supply current, at least one of the groups including at least two rows connected in parallel so as to distribute the supply current between the at least two rows.
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