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公开(公告)号:US20240268239A1
公开(公告)日:2024-08-08
申请号:US18430427
申请日:2024-02-01
Inventor: Fabrice NEMOUCHI , Francois LEFLOCH , Shi-Li ZHANG , Zhen ZHANG
CPC classification number: H10N60/128 , H10N60/0912
Abstract: Method for producing a superconducting transistor comprising:
producing a dummy gate on a first part of a semiconducting layer;
producing superconducting electrodes such that the first part of the semiconducting layer comprises sides edges arranged against parts of the superconducting electrodes, and comprising a deposition of a superconducting material layer having first parts arranged against side edges of the dummy gate and second parts forming parts of the superconducting electrodes;
producing lateral spacers next to the first parts of the superconducting material layer and on the second parts of the superconducting material layer;
removing the dummy gate and the first parts of the superconducting material layer, creating a gate location arranged between the lateral spacers and above the first part of the semiconducting layer and above said parts of the superconducting electrodes;
producing a gate in the gate location.