公开(公告)号：US20200185497A1

公开(公告)日：2020-06-11

申请号：US16699384

申请日：2019-11-29

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Nicolas POSSEME ,  Louis HUTIN ,  Cyrille LE ROYER ,  Fabrice NEMOUCHI

IPC: H01L29/12 ,  H01L29/417 ,  H03K17/567

Abstract: A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided.

公开(公告)号：US20150311287A1

公开(公告)日：2015-10-29

申请号：US14695787

申请日：2015-04-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Fabrice NEMOUCHI ,  Emilie BOURJOT

IPC: H01L29/10 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/31051 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

Abstract: Fabrication of a field-effect transistor is performed on a substrate comprising a film made from first semiconductor material, a gate dielectric covered by a gate electrode, source and drain areas separated by the gate electrode, a protection layer covering gate electrode and source and drain areas, and an access hole to the source area and/or to drain area. Metallic material is deposited in the access hole in contact with the first semiconductor material of the source and/or drain area. An electrically conducting barrier layer that is non-reactive with the first semiconductor material and with the metallic material is deposited before reaction of metallic material with first semiconductor material. Transformation heat treatment of the metallic material with the semiconductor material is performed to form a metallic material having a base formed by the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas.

Abstract translation: 在包括由第一半导体材料制成的膜，由栅电极覆盖的栅极电介质，由栅极电极分离的源极和漏极区域的衬底，覆盖栅电极的保护层和源极和漏极的衬底上进行场效应晶体管的制造 区域，以及到源区和/或排水区的通孔。 金属材料沉积在与源极和/或漏极区域的第一半导体材料接触的入口孔中。 在金属材料与第一半导体材料反应之前，沉积与第一半导体材料和金属材料不反应的导电阻挡层。 进行具有半导体材料的金属材料的变形热处理，以形成具有由半导体材料形成的基底的金属材料，该基底在布置在源极和漏极区域之间的导电通道上产生一组应力。

公开(公告)号：US20230210021A1

公开(公告)日：2023-06-29

申请号：US18056318

申请日：2022-11-17

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Cyrille LE ROYER ,  Fabrice NEMOUCHI ,  Roselyne SEGAUD

IPC: H10N60/85 ,  H10N60/01

CPC classification number: H10N60/85 ,  H10N60/0156

Abstract: The invention concerns an inteconnect device for interconnection between lines of superconducting material at least one via in contact with those lines, comprising:
a) a first substrate, which carries at least one first line of a first superconducting material;

b) at least one first via of a second superconducting material, different from the first superconducting material, said at least one first line being disposed between said first substrate and said first via;

c) at least one second line above said first via and in contact with the latter.

公开(公告)号：US20190187375A1

公开(公告)日：2019-06-20

申请号：US16226470

申请日：2018-12-19

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Fabrice NEMOUCHI ,  Charles BAUDOT ,  Yann BOGUMILOWICZ ,  Elodie GHEGIN ,  Philippe RODRIGUEZ

IPC: G02B6/13 ,  G02B6/122

CPC classification number: G02B6/131 ,  G02B6/1225 ,  G02B2006/12061 ,  G02B2006/12121 ,  G02B2006/12128 ,  G02B2006/1213 ,  G02B2006/12142 ,  G02B2006/12178 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L25/0753 ,  H01L33/0066 ,  H01L33/0079

Abstract: A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elements and/or active elements, the interface being produced on the surface of a second silicon-based substrate; removing the first silicon-based substrate and the at least elementary base layer located on the elementary structure.

公开(公告)号：US20190006182A1

公开(公告)日：2019-01-03

申请号：US16024008

申请日：2018-06-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Philippe RODRIGUEZ ,  Seifeddine ZHIOU ,  Fabrice NEMOUCHI ,  Patrice GERGAUD

IPC: H01L21/283 ,  H01L29/45 ,  H01L29/40

CPC classification number: H01L21/283 ,  H01L21/28575 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/452

Abstract: A process for manufacturing an intermetallic contact on the surface of a layer or of a substrate of oriented InxGa1-xAs material, the contact includes an Ni—InGaAs intermetallic compound, the intermetallic compound having a hexagonal crystallographic structure that may have: a first texture or a second texture formed at a second nucleation temperature above the first nucleation temperature; the process comprising the following steps: the production of nomograms defining, for a thickness of Ni deposited, the time to completely consume the initial thickness of Ni as a function of the annealing temperature, the annealing temperature being below the nucleation temperature of the second texture; the localized deposition of Ni on the surface of the InxGa1-xAs material; an annealing step applying the pair of parameters: time required/annealing temperature, deduced from the nomograms, comprising at least one temperature rise step and at least one temperature hold of the final annealing temperature.

公开(公告)号：US20170062424A1

公开(公告)日：2017-03-02

申请号：US15234240

申请日：2016-08-11

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe RODRIGUEZ ,  Elodie GHEGIN ,  Fabrice NEMOUCHI

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02068 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/8258 ,  H01L29/161 ,  H01L29/45 ,  H01L29/66568

Abstract: A production of contact zones for a transistor device including the steps of: a) forming at least one layer made of a compound based on semiconductor and metal on one or more first semiconductor region(s) of a first N-type transistor and on one or more second semiconductor region(s) of a second P-type transistor resting on a same substrate, the first regions being based on a III-V type material whereas the second semiconductor regions are based on another material different from the III-V material, the semiconductor of the compound being an N-type dopant of the III-V material, b) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while increasing the N-doping of the III-V material.

公开(公告)号：US20220172093A1

公开(公告)日：2022-06-02

申请号：US17456388

申请日：2021-11-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Louis HUTIN ,  Cyrille LE ROYER ,  François LEFLOCH ,  Fabrice NEMOUCHI ,  Maud VINET

IPC: G06N10/00 ,  H01L39/22 ,  H01L39/24 ,  H01L29/66

Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

公开(公告)号：US20170162672A1

公开(公告)日：2017-06-08

申请号：US15372930

申请日：2016-12-08

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Louis HUTIN ,  Julien BORREL ,  Yves MORAND ,  Fabrice NEMOUCHI

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66643 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/7839

Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.

公开(公告)号：US20170117186A1

公开(公告)日：2017-04-27

申请号：US15335092

申请日：2016-10-26

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Claire FENOUILLET-BERANGER ,  Fabrice NEMOUCHI

IPC: H01L21/822 ,  H01L21/768

CPC classification number: H01L21/8221 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53271 ,  H01L27/0688

Abstract: Fabrication of an integrated circuit comprising: at least one first transistor made at least partially in a first semiconducting layer, at least one second transistor made at least partially in a second semiconducting layer formed above the first semiconducting layer, an insulating layer formed between the first transistor and the second transistor, one or several connection elements passing through the insulating layer between the first and the second transistor, at least one connection element being connected to the first and/or the second transistor and being based on a metal—semiconductor alloy.

公开(公告)号：US20240268239A1

公开(公告)日：2024-08-08

申请号：US18430427

申请日：2024-02-01

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Fabrice NEMOUCHI ,  Francois LEFLOCH ,  Shi-Li ZHANG ,  Zhen ZHANG

IPC: H10N60/10 ,  H10N60/01

CPC classification number: H10N60/128 ,  H10N60/0912

Abstract: Method for producing a superconducting transistor comprising:



producing a dummy gate on a first part of a semiconducting layer;
producing superconducting electrodes such that the first part of the semiconducting layer comprises sides edges arranged against parts of the superconducting electrodes, and comprising a deposition of a superconducting material layer having first parts arranged against side edges of the dummy gate and second parts forming parts of the superconducting electrodes;
producing lateral spacers next to the first parts of the superconducting material layer and on the second parts of the superconducting material layer;
removing the dummy gate and the first parts of the superconducting material layer, creating a gate location arranged between the lateral spacers and above the first part of the semiconducting layer and above said parts of the superconducting electrodes;
producing a gate in the gate location.